CSE460t Wiki FA17_cse460t_wiki http://classes.engineering.wustl.edu/cse460t/index.php?title=Main_Page MediaWiki 1.34.4 first-letter Media Special Talk User User talk CSE460t Wiki CSE460t Wiki talk File File talk MediaWiki MediaWiki talk Template Template talk Help Help talk Category Category talk 0 1 1 2009-08-14T10:45:04Z MediaWiki default 0 wikitext text/x-wiki <big>'''MediaWiki has been successfully installed.'''</big> Consult the [http://meta.wikimedia.org/wiki/Help:Contents User's Guide] for information on using the wiki software. == Getting started == * [http://www.mediawiki.org/wiki/Manual:Configuration_settings Configuration settings list] * [http://www.mediawiki.org/wiki/Manual:FAQ MediaWiki FAQ] * [https://lists.wikimedia.org/mailman/listinfo/mediawiki-announce MediaWiki release mailing list] bd962048d95fbb6b6b514885867811db20a5476b 2 1 2009-11-11T22:25:25Z WikiSysop 1 wikitext text/x-wiki <center><big> CSE462M COMPUTER SYSTEM DESIGN </big> ''Spring 2009'' ''William D. Richard, Ph.D.'' --- Tuesday/Thursday, 1:00 - 2:30 p.m. 45d9edd11da5202b0481e9c20f0256b558c25b66 3 2 2009-11-11T22:25:44Z WikiSysop 1 wikitext text/x-wiki <center><big> CSE462M COMPUTER SYSTEM DESIGN </big> ''Spring 2009'' ''William D. Richard, Ph.D.'' --- Tuesday/Thursday, 1:00 - 2:30 p.m. 617cb87eb826388f804261f7e34afa7e796c8e4c 4 3 2009-11-11T22:31:03Z WikiSysop 1 wikitext text/x-wiki <center> <font size=10>CSE462M COMPUTER SYSTEM DESIGN </font> ''Spring 2009'' ''William D. Richard, Ph.D.'' --- Tuesday/Thursday, 1:00 - 2:30 p.m. </center> a0f337034db97e81043c739b5f5bd0488cab0d3f 5 4 2009-11-11T22:32:57Z WikiSysop 1 wikitext text/x-wiki <center><b> <font size=6>CSE462M COMPUTER SYSTEM DESIGN </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' == Tuesday/Thursday, 1:00 - 2:30 p.m. </b> </center> 12d5d54c65c9576829d9006de44797de53a25388 6 5 2009-11-11T22:33:04Z WikiSysop 1 wikitext text/x-wiki <center><b> <font size=6>CSE462M COMPUTER SYSTEM DESIGN </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' === Tuesday/Thursday, 1:00 - 2:30 p.m. </b> </center> b8549d70162fc2c8d5a538863c4b755578502e10 7 6 2009-11-11T22:33:15Z WikiSysop 1 wikitext text/x-wiki <center><b> <font size=6>CSE462M COMPUTER SYSTEM DESIGN </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' == Tuesday/Thursday, 1:00 - 2:30 p.m. </b> </center> 976fd92e35083c789db3eff4e97d4b662c1deb08 8 7 2009-11-11T22:33:22Z WikiSysop 1 wikitext text/x-wiki <center><b> <font size=6>CSE462M COMPUTER SYSTEM DESIGN </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' = Tuesday/Thursday, 1:00 - 2:30 p.m. </b> </center> 788ce6993b04561e923dd5b82866afdf75d9ab9d 9 8 2009-11-11T22:34:21Z WikiSysop 1 wikitext text/x-wiki <center><b> <font size=6>CSE462M COMPUTER SYSTEM DESIGN </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' ---- Tuesday/Thursday, 1:00 - 2:30 p.m. </b> </center> 445a06a30cffcac5404a16b01289ab75e34c4ad1 10 9 2009-11-11T22:34:55Z WikiSysop 1 wikitext text/x-wiki <center> <font size=6>'''CSE462M''' '''COMPUTER SYSTEM DESIGN''' </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' 296833fef41087fe7027e2e126d0b71e1af766ef 62 10 2009-11-12T14:04:19Z WikiSysop 1 wikitext text/x-wiki <center> <font size=6>'''CSE462M''' '''COMPUTER SYSTEM DESIGN''' </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' ---- Capstone Computer Engineering Design Course. Prerequisites: CSE 361S, CSE 362M 03ad0c21cceea99cf69af6371099b668dac4d602 63 62 2009-11-12T14:04:30Z WikiSysop 1 wikitext text/x-wiki <center> <font size=6>'''CSE462M''' '''COMPUTER SYSTEM DESIGN''' </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' ---- Capstone Computer Engineering Design Course. Prerequisites: CSE 361S, CSE 362M ee2383439c3500aa410b5c9f3bfb3d32aba437c6 100 63 2009-11-12T14:40:51Z WikiSysop 1 wikitext text/x-wiki <center> <font size=6>'''CSE462M''' '''COMPUTER SYSTEM DESIGN''' </font> <font size=3> '''Spring 2009''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' ---- Capstone Computer Engineering Design Course. Prerequisites: CSE 361S, CSE 362M 5d6461b2175290aaf32ea74ac539e2fa04f3a9ba 8 2 11 2009-11-11T22:36:18Z WikiSysop 1 Created page with '* Information ** Course Description ** General Information ** Syllabus ** Graders * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currente…' wikitext text/x-wiki * Information ** Course Description ** General Information ** Syllabus ** Graders * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help * SEARCH * TOOLBOX * LANGUAGES 56111817bbf6ab53b911bf00164a3c75c0b78abd 17 11 2009-11-11T22:42:35Z WikiSysop 1 wikitext text/x-wiki * Information ** Course Description|Course Description ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help * SEARCH * TOOLBOX * LANGUAGES 0ba2de1c7ffadd48d2419b2c0b42effb1d246e97 18 17 2009-11-11T22:43:15Z WikiSysop 1 wikitext text/x-wiki * Information ** Course Description|Course Description ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Other Links ** Cypress|http://www.cypress.com * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help * SEARCH * TOOLBOX * LANGUAGES 976b8cf254fd117e184a4661f3310d78d7e9f9ec 19 18 2009-11-11T22:43:35Z WikiSysop 1 wikitext text/x-wiki * Information ** Course Description|Course Description ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Other Links ** http://www.cypress.com|Cypress * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help * SEARCH * TOOLBOX * LANGUAGES 0d308bbd3d55bdad761672ff02e19aae54aaf3a9 20 19 2009-11-11T22:44:35Z WikiSysop 1 wikitext text/x-wiki * Information ** Course Description|Course Description ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Other Links ** http://www.cypress.com|Cypress ** http://www.ftdichip.com|Future Technology Devices Intl. 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Ltd ** http://www.dlpdesign.com|DLP Design ** http://www.usb.org|USB Implementers Forum ** http://1394ta.org|1394 Trade Association ** http://www.pcisig.org|PCI Special Interest Group * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 1302e3ccfbbf73b5b819e5eb62a76cdbba3bc7c8 101 64 2009-12-01T16:32:14Z WikiSysop 1 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets ** Other Links|Other Links * Historical ** http://www.islandnet.com/~kpolsson/comphist|Chronology of Computers ** http://vmoc.museophile.com|Virtual Museum of Computing * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 41884b840d77c5ef1fefb3bf2d34361e9c32c4ec 102 101 2009-12-01T16:32:43Z WikiSysop 1 Undo revision 101 by [[Special:Contributions/WikiSysop|WikiSysop]] ([[User talk:WikiSysop|Talk]]) wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://www.cypress.com|Cypress ** http://www.ftdichip.com|Future Technology Devices Intl. Ltd ** http://www.dlpdesign.com|DLP Design ** http://www.usb.org|USB Implementers Forum ** http://1394ta.org|1394 Trade Association ** http://www.pcisig.org|PCI Special Interest Group * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 1302e3ccfbbf73b5b819e5eb62a76cdbba3bc7c8 0 3 12 2009-11-11T22:36:45Z WikiSysop 1 Created page with 'Dr. Richard will personally grade all homework this semester.' wikitext text/x-wiki Dr. Richard will personally grade all homework this semester. 38c40662b6e50d568df473273eea0935c8bc546a 0 4 13 2009-11-11T22:37:10Z WikiSysop 1 Created page with 'Capstone Computer Engineering Design Course. Prerequisites: CSE 361S, CSE 362M' wikitext text/x-wiki Capstone Computer Engineering Design Course. Prerequisites: CSE 361S, CSE 362M 5eee4503c13533633b9dd628dcd26bae062552d9 0 5 14 2009-11-11T22:37:47Z WikiSysop 1 Created page with 'Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http:/…' wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m. Cupples II 220 Mid-term Exam: TBD Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. a41e9c01e456e162d7534640f8b7a44ae87a5537 103 14 2009-12-29T17:27:36Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m. Lopata 302 Mid-term Exam: TBD Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 440bcc25ffdf38f124c29f0dfaa4fe24a979ede6 0 6 15 2009-11-11T22:38:10Z WikiSysop 1 Created page with ' 1. The Universal Serial Bus 1. The Universal Serial Bus V1.1 and V2.0 2. The FTDI and Cypress USB Chips 3. Prototype Boards 2. FPGAs …' wikitext text/x-wiki 1. The Universal Serial Bus 1. The Universal Serial Bus V1.1 and V2.0 2. The FTDI and Cypress USB Chips 3. Prototype Boards 2. FPGAs 1. Actel and Xilinx FPGAs 2. Tool Support 3. Development Scripts 3. VHDL 1. VHDL Review 2. Synthesizable VHDL 4. Semester Project Requirements 1. Requirements 2. Basic Block Diagram 3. Testing 5. Advanced Topics 1. PCI 2. Firewire 6. Professional and Ethical Responsibilities, Lifelong Learning 1. ACM Code of Ethics 2. IEEE Code of Ethics 3. Lifelong Learning 4b24c52f9151a4cf7001dd63cda56377be1eff6d 16 15 2009-11-11T22:39:51Z WikiSysop 1 wikitext text/x-wiki # The Universal Serial Bus ## The Universal Serial Bus V1.1 and V2.0 ## The FTDI and Cypress USB Chips ## Prototype Boards # FPGAs ## Actel and Xilinx FPGAs ## Tool Support ## Development Scripts # VHDL ## VHDL Review ## Synthesizable VHDL # Semester Project Requirements ## Requirements ## Basic Block Diagram ## Testing # Advanced Topics ## PCI ## Firewire # Professional and Ethical Responsibilities, Lifelong Learning ## ACM Code of Ethics ## IEEE Code of Ethics ## Lifelong Learning 05b60c5bf135e85e88bf839b08a35aea7994d61d 0 30 46 2009-11-11T23:21:19Z WikiSysop 1 Created page with ' * [[ADC Construction|File:ADC Construction.pdf]]' wikitext text/x-wiki * [[ADC Construction|File:ADC Construction.pdf]] 401c9d19e4aeddac1bd722f349139664886b8f4f 47 46 2009-11-11T23:21:40Z WikiSysop 1 wikitext text/x-wiki * [[File:ADC Construction.pdf||ADC Construction]] 6a71f8344b14cdadb3ead87876520a2b75a155b2 51 47 2009-11-11T23:35:06Z WikiSysop 1 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:ADC Construction.pdf|ADC Construction File:ics57001-2.pdf|Clock Multiplier 1 File:ics67004.pdf|Clock Multiplier 2 File:ics6720102-1.pdf|Clock Multiplier 3 </gallery> 29cb2f0b469cd4be5cc0c17ff882fce60c3f6c5c 52 51 2009-11-11T23:36:34Z WikiSysop 1 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:ADC Construction.pdf|ADC Construction File:ics57001-2.pdf|Clock Multiplier 1 File:ics67004.pdf|Clock Multiplier 2 File:ics6720102-1.pdf|Clock Multiplier 3 File:Test Code.txt|Timing Test Code File:AGL125V5 Timing Results.bmp|Actel Igloo AGL125V5 Timing Results File:AGLN250V5Z Timing Results.bmp|Actel Igloo Nano AGLN250V5Z Timing Results </gallery> a118acea904cd008266a6287b96c3586efe43810 53 52 2009-11-11T23:43:31Z WikiSysop 1 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:ADC Construction.pdf|ADC Construction File:ics57001-2.pdf|Clock Multiplier 1 File:ics67004.pdf|Clock Multiplier 2 File:ics6720102-1.pdf|Clock Multiplier 3 File:Test Code.txt|Timing Test Code File:AGL125V5 Timing Results.bmp|Actel Igloo AGL125V5 Timing Results File:AGLN250V5Z Timing Results.bmp|Actel Igloo Nano AGLN250V5Z Timing Results File:xc3s200_top.twr|Xilinx XC3S200 Timing Results File:xc3s200an_top.twr|Xilinx XC3S200AN Timing Results File:comparator test.vhd|Comparator Timing Test Code File:AGLN250V5Z Comparator Timing Results.bmp|Actel Igloo Nano AGLN250V5Z Timing Results File:xc3s200an_comp_top.twr|Xilinx XC3S200AN Timing Results File:S3 ADC Adapter.pdf|Scope Frontend Strawman File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:TUTORIAL.pdf|FTDI Software Tutorial File:ftdiTest.zip|FTDI Software Tutorial Source File:462.zip|MPROG Template File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics [[http://http://www.acm.org/constitution/code.html]] File:Employment Contract - Clean.pdf|Employment Contract File:Prices.xlsx|Price Estimate (Excel) File:Prices.pdf|Price Estimate (PDF) </gallery> 0848b8929a6adc624b3e62ca3436686181e946d3 54 53 2009-11-11T23:45:57Z WikiSysop 1 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:ADC Construction.pdf|ADC Construction File:ics57001-2.pdf|Clock Multiplier 1 File:ics67004.pdf|Clock Multiplier 2 File:ics6720102-1.pdf|Clock Multiplier 3 File:Test Code.txt|Timing Test Code File:AGL125V5 Timing Results.bmp|Actel Igloo AGL125V5 Timing Results File:AGLN250V5Z Timing Results.bmp|Actel Igloo Nano AGLN250V5Z Timing Results File:xc3s200_top.twr|Xilinx XC3S200 Timing Results File:xc3s200an_top.twr|Xilinx XC3S200AN Timing Results File:comparator test.vhd|Comparator Timing Test Code File:AGLN250V5Z Comparator Timing Results.bmp|Actel Igloo Nano AGLN250V5Z Timing Results File:xc3s200an_comp_top.twr|Xilinx XC3S200AN Timing Results File:S3 ADC Adapter.pdf|Scope Frontend Strawman File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:TUTORIAL.pdf|FTDI Software Tutorial File:ftdiTest.zip|FTDI Software Tutorial Source File:462.zip|MPROG Template File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract File:Prices.xlsx|Price Estimate (Excel) File:Prices.pdf|Price Estimate (PDF) </gallery> <font size=4> Links: [http://http://www.acm.org/constitution/code.html| ACM Code of Ethics] </font> b5aed0769eb027c3ca774ed98e7943435e080821 104 54 2009-12-29T18:47:08Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://http://www.acm.org/constitution/code.html| ACM Code of Ethics] </font> 7359f03075bf1f04804ba4d12db57e3ef12a54d3 105 104 2009-12-29T18:48:11Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.ieee.org/portal/pages/iportals/aboutus/ethics/code.html| ACM Code of Ethics] </font> 067a44dba1966fcfa7467d04b98d7369efaac06e 106 105 2009-12-29T18:49:55Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> 5452d0c41fc9fa9c711a60fb9b5dd7a928577a20 0 35 59 2009-11-11T23:52:31Z WikiSysop 1 Created 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text/x-wiki <gallery> Nov 1 09 057.jpg|Mid-term </gallery> 14d2044776b5c17f5866585103c69f6d45ac9374 0 46 73 2009-11-12T14:20:55Z WikiSysop 1 Created page with '<gallery perrow="1"> File:Groups.pdf|PROJECT GROUPS File:SPRING 2009 PROJECT ASSIGNMENT.pdf|PROJECT ASSIGNMENT File:Gantt Chart [Compatibility Mode].pdf|PROJECT GANTT CHART File:…' wikitext text/x-wiki <gallery perrow="1"> File:Groups.pdf|PROJECT GROUPS File:SPRING 2009 PROJECT ASSIGNMENT.pdf|PROJECT ASSIGNMENT File:Gantt Chart [Compatibility Mode].pdf|PROJECT GANTT CHART File:SPRING 2009 PAPER.pdf|PROJECT PAPER ASSIGNMENT File:cse462_group3.ppt|Example Presentation PPT File:cse462_group3.pdf|Example Presentation PDF File:1991 Vision System.pdf|Example Paper File:backend.zip|Fake Backend </gallery> e4185639e63abdd1bebd1976767c59b79cb3c322 74 73 2009-11-12T14:21:09Z WikiSysop 1 wikitext text/x-wiki <gallery> File:Groups.pdf|PROJECT GROUPS File:SPRING 2009 PROJECT ASSIGNMENT.pdf|PROJECT ASSIGNMENT File:Gantt Chart [Compatibility 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Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> 41d819ad4fadb056ce88db92a117df763ea5f009 145 144 2010-01-26T15:07:24Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Software User Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> 4f34c31ead5f952da2ed78eb57e7276d844bec83 146 145 2010-01-26T15:08:52Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Software User Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> ef63ade0f0bf23fd2991ff4b29499ff39924a720 147 146 2010-01-26T15:09:12Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> d190934b4e3f831f493afaa3420c704545c7af86 150 147 2010-01-26T15:11:05Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> 490e94916ef320720915dfa17962d0bf91bae835 151 150 2010-01-26T15:13:02Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> b782523a8d1cf0c7293ac1416aea16087a535ace 152 151 2010-01-26T15:15:49Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> 01ceb878c8a6e4d20405bb545b5eafb84a34d598 155 152 2010-01-26T15:17:07Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:DS FT2232H V206.pdf|FTDI FT2232H Datasheet File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> d26c5aefbd033b792fbb24f706a9097ab5e998bb 156 155 2010-01-26T15:17:49Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:DS FT2232H V206.pdf|FTDI FT2232H Datasheet File:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> 47c00e4c550f94eec0e106b334f0b188c788cc32 162 156 2010-01-26T15:39:53Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:DS FT2232H V206.pdf|FTDI FT2232H Datasheet File:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OV7620.pdf|Omnivision OVM7620 Datasheet File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> b9140828590d982b2bf43de969a66b058561af0d 163 162 2010-01-26T15:40:52Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:DS FT2232H V206.pdf|FTDI FT2232H Datasheet File:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OV7620.pdf|Omnivision OVM7620 Datasheet File:C3188A.pdf|C3188A Camera Module File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> 47b79cc4c0339cba199720f9af461c7d95e131b6 164 163 2010-01-26T15:41:26Z Wdr 2 wikitext text/x-wiki <gallery> File:usb_20.pdf|USB 2.0 Specification File:DS FT2232H V206.pdf|FTDI FT2232H Datasheet File:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OV7620.pdf|Omnivision OVM7620 Datasheet File:C3188A.pdf|C3188A Camera Module File:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> aadccfcea1c05156cd6cf7a9093091203378fe66 165 164 2010-01-26T15:44:41Z Wdr 2 wikitext text/x-wiki *[[media:usb_20.pdf|USB 2.0 Specification]] <gallery> File:usb_20.pdf|USB 2.0 Specification File:DS FT2232H V206.pdf|FTDI FT2232H Datasheet File:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet File:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual File:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor File:OV7620.pdf|Omnivision OVM7620 Datasheet File:C3188A.pdf|C3188A Camera Module File:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic File:OVM7690.pdf|OmniVision OVM7690 File:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet File:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide File:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide File:Cy7c68013a 8-2.pdf|Cypress CY7C68013A File:Cp2102-1.pdf|Silicon Labs CP2102 File:Xps usb2 device.pdf|Xilinx USB Core File:DS FT2232D.pdf|FTDI FT2232D File:Dlp2232m-v15-ds.pdf|DLP 2232M-G File:DS FT245BM.pdf|FTDI FT245BM File:Dlp-usb245mv15.pdf|DLP USB245M File:Pci 23.pdf|PCI 2.3 Specification File:Ds099.pdf|Xilinx Spartan 3 FPGA File:Ds557.pdf|Xilinx Spartan 3AN FPGA File:IGLOO HB.pdf|Actel Igloo FPGA File:TDS 340A Manual.pdf|TDS 340A Manual File:S3BOARD-brochure.pdf|Digilent S3 Board Brochure File:S3BOARD-rm.pdf|Digilent S3 Board User's Guide File:S3BOARD-sch.pdf|Digilent S3 Board Schematic File:S3 Adapter Schematic.pdf|S3 Adapter Schematic File:ExpressPCB Layout.bmp|S3 Adapter Layout File:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet File:PI6C4511.pdf|PI6C4511 File:NB3L553-D.pdf|NB3L553 </gallery> c029e5d98e27a8fb9f3ceb9061e43f3f2771c4a9 166 165 2010-01-26T16:15:28Z Wdr 2 wikitext text/x-wiki *[[media:usb_20.pdf|USB 2.0 Specification]] *[[media:usb_20.pdf|USB 2.0 Specification]] *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] *[[media:C3188A.pdf|C3188A Camera Module]] *[[media:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic]] *[[media:OVM7690.pdf|OmniVision OVM7690]] *[[media:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet]] *[[media:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide]] *[[media:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide]] *[[media:Cy7c68013a 8-2.pdf|Cypress CY7C68013A]] *[[media:Cp2102-1.pdf|Silicon Labs CP2102]] *[[media:Xps usb2 device.pdf|Xilinx USB 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Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 3c0104347c40aa1ffd63ff54d493c477068a4635 172 167 2010-01-28T16:12:54Z Wdr 2 wikitext text/x-wiki *[[media:usb_20.pdf|USB 2.0 Specification]] *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:D2XX Programmers Guide.pdf|D2XX Programmer's Guide]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] *[[media:C3188A.pdf|C3188A Camera Module]] *[[media:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic]] *[[media:OVM7690.pdf|OmniVision OVM7690]] *[[media:OVM7690_MDS_2.4.pdf|OmniVision OVM7690 Datasheet]] *[[media:Evaluation Module QSG (1.0)ECJA.PDF|OVM7690 Evaluation Module Quick Start Guide]] *[[media:OVTATool Lite User Guide.pdf|OVM7690 Evaluation Module Software User Guide]] *[[media:Cy7c68013a 8-2.pdf|Cypress CY7C68013A]] *[[media:Cp2102-1.pdf|Silicon Labs CP2102]] *[[media:Xps usb2 device.pdf|Xilinx USB Core]] *[[media:DS FT2232D.pdf|FTDI FT2232D]] *[[media:Dlp2232m-v15-ds.pdf|DLP 2232M-G]] *[[media:DS FT245BM.pdf|FTDI FT245BM]] *[[media:Dlp-usb245mv15.pdf|DLP USB245M]] *[[media:Pci 23.pdf|PCI 2.3 Specification]] *[[media:Ds099.pdf|Xilinx Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 064cb085628f9f04f4e7eccd0d3501379d26a2ea 177 172 2010-01-29T15:26:06Z Wdr 2 wikitext text/x-wiki *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:D2XX Programmers Guide.pdf|D2XX Programmer's Guide]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] *[[media:C3188A.pdf|C3188A Camera Module]] *[[media:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic]] *[[media:OVM7690.pdf|OmniVision OVM7690]] *[[media:Cy7c68013a 8-2.pdf|Cypress CY7C68013A]] *[[media:Cp2102-1.pdf|Silicon Labs CP2102]] *[[media:Xps usb2 device.pdf|Xilinx USB Core]] *[[media:DS FT2232D.pdf|FTDI FT2232D]] *[[media:Dlp2232m-v15-ds.pdf|DLP 2232M-G]] *[[media:DS FT245BM.pdf|FTDI FT245BM]] *[[media:Dlp-usb245mv15.pdf|DLP USB245M]] *[[media:Pci 23.pdf|PCI 2.3 Specification]] *[[media:Ds099.pdf|Xilinx Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 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Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' ---- Capstone Computer Engineering Design Course. Prerequisites: CSE 361S, CSE 362M ef1063657d37a86a3717fd09a8ff5bad5bee4261 0 30 116 106 2010-01-06T20:46:02Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notess"> File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> ba1bf5d307427a6a3715357fe31bb0b2e75c3108 117 116 2010-01-06T20:46:13Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> 5452d0c41fc9fa9c711a60fb9b5dd7a928577a20 130 117 2010-01-21T14:38:15Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:Stereo Vision|Stereo_Vision.PDF File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> 556149f9682c198cb70a4a02299102a7f1a7c394 131 130 2010-01-21T14:38:28Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:Stereo Vision|Stereo Vision.PDF File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> 2185202dc4a723f004d40c253e86062c30bed172 132 131 2010-01-21T14:38:56Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:Stereo Vision.PDF|Stereo Vision File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> d0ba36f8dba9830a553f8fc75c294ed57712c2a5 133 132 2010-01-21T14:39:07Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:Stereo_Vision.PDF|Stereo Vision File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> b338c286f9c80a133f37678dd1e11822b4d07107 134 133 2010-01-21T14:40:09Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:Stereo_Vision.pdf|Stereo Vision File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> d8e20504aacadaa3d6c5e1edc743affc11d6f930 176 134 2010-01-28T18:49:14Z Wdr 2 wikitext text/x-wiki <gallery caption="Lecture Notes"> File:Adapter Schematic.pdf |Adapter Schematic File:Stereo_Vision.pdf|Stereo Vision File:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture File:Paper1.pdf|Metastability 1 File:Paper2.pdf|Metastability 2 File:ieee_codeofethics.pdf|IEEE Code of Ethics File:Employment Contract - Clean.pdf|Employment Contract </gallery> <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> f26cf10982271b0628ae1453910b7c98b0824bfe 178 176 2010-01-29T15:29:15Z Wdr 2 wikitext text/x-wiki *[[media:Adapter Schematic.pdf |Adapter Schematic]] *[[media:Stereo_Vision.pdf|Stereo Vision]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Paper1.pdf|Metastability 1]] *[[media:Paper2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] <font size=4> Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] </font> 0c1c867214d398c1f353d3b237b17dcc9a90cb0a 8 2 118 102 2010-01-11T16:09:21Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** xrated|xrated ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://www.cypress.com|Cypress ** http://www.ftdichip.com|Future Technology Devices Intl. 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HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 7f1c959128dc9c8f5817ed3fbab43d8e8344389d 192 191 2010-02-01T16:03:35Z Wdr 2 wikitext text/x-wiki *[[media:I2C Specification.pdf|I2C Specification]] *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:D2XX Programmers Guide.pdf|D2XX Programmer's Guide]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] 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Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] edbed937f49ae5fd09e1df49eb8e41a1f46775d3 200 192 2010-02-04T14:09:07Z Wdr 2 wikitext text/x-wiki *[[media:Digilent Spartan 3E Starter Board Schematic.pdf|Digilent Spartan 3E Starter Board Schematic]] *[[media:Digilent Spartan 3E Starter Board User Guide.pdf|Digilent Spartan 3E Starter Board User Guide]] *[[media:I2C Specification.pdf|I2C Specification]] *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:D2XX Programmers Guide.pdf|D2XX Programmer's Guide]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] *[[media:C3188A.pdf|C3188A Camera Module]] *[[media:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic]] *[[media:OVM7690.pdf|OmniVision OVM7690]] *[[media:Cy7c68013a 8-2.pdf|Cypress CY7C68013A]] *[[media:Cp2102-1.pdf|Silicon Labs CP2102]] *[[media:Xps usb2 device.pdf|Xilinx USB Core]] *[[media:DS FT2232D.pdf|FTDI FT2232D]] *[[media:Dlp2232m-v15-ds.pdf|DLP 2232M-G]] *[[media:DS FT245BM.pdf|FTDI FT245BM]] *[[media:Dlp-usb245mv15.pdf|DLP USB245M]] *[[media:Pci 23.pdf|PCI 2.3 Specification]] *[[media:Ds099.pdf|Xilinx Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 8d7a6f207c7ec28e0c4bd96bf7596c74d46744d2 215 200 2010-02-09T14:19:15Z Wdr 2 wikitext text/x-wiki *[[media:Ds312.pdf|Spartan 3E FPGA Datasheet]] *[[media:Digilent Spartan 3E Starter Board Schematic.pdf|Digilent Spartan 3E Starter Board Schematic]] *[[media:Digilent Spartan 3E Starter Board User Guide.pdf|Digilent Spartan 3E Starter Board User Guide]] *[[media:I2C Specification.pdf|I2C Specification]] *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:D2XX Programmers Guide.pdf|D2XX Programmer's Guide]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] *[[media:C3188A.pdf|C3188A Camera Module]] *[[media:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic]] *[[media:OVM7690.pdf|OmniVision OVM7690]] *[[media:Cy7c68013a 8-2.pdf|Cypress CY7C68013A]] *[[media:Cp2102-1.pdf|Silicon Labs CP2102]] *[[media:Xps usb2 device.pdf|Xilinx USB Core]] *[[media:DS FT2232D.pdf|FTDI FT2232D]] *[[media:Dlp2232m-v15-ds.pdf|DLP 2232M-G]] *[[media:DS FT245BM.pdf|FTDI FT245BM]] *[[media:Dlp-usb245mv15.pdf|DLP USB245M]] *[[media:Pci 23.pdf|PCI 2.3 Specification]] *[[media:Ds099.pdf|Xilinx Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 26134e2e1f1f0089f8c2549c1a9a5555c6ad0d94 229 215 2010-02-11T16:03:40Z Wdr 2 wikitext text/x-wiki *[[media:AP2141_51.pdf|AP2141 Power Switch]] *[[media:Ds312.pdf|Spartan 3E FPGA Datasheet]] *[[media:Digilent Spartan 3E Starter Board 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*[[media:Dlp-usb245mv15.pdf|DLP USB245M]] *[[media:Pci 23.pdf|PCI 2.3 Specification]] *[[media:Ds099.pdf|Xilinx Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] b82e1af22d0a4d13f1f91cf60dba16acd7282950 250 229 2010-02-16T13:12:52Z Wdr 2 wikitext text/x-wiki *[[media:MCP1700.pdf‎|MCP1700 Linear Regulator]] *[[media:AP2141_51.pdf|AP2141 Power Switch]] *[[media:Ds312.pdf|Spartan 3E FPGA Datasheet]] *[[media:Digilent Spartan 3E Starter Board Schematic.pdf|Digilent Spartan 3E Starter Board Schematic]] *[[media:Digilent Spartan 3E Starter Board User Guide.pdf|Digilent Spartan 3E Starter Board User Guide]] *[[media:I2C Specification.pdf|I2C Specification]] *[[media:DS FT2232H V206.pdf|FTDI FT2232H Datasheet]] *[[media:DS FT2232H Mini Module.pdf|FT2232H Mini Module Datasheet]] *[[media:D2XX Programmers Guide.pdf|D2XX Programmer's Guide]] *[[media:SparkFun Cameral Manual.pdf|SparkFun Cameral Manual]] *[[media:HV7131GP.pdf|MagnaChip HV7131GP CMOS Image Sensor]] *[[media:OV7620.pdf|Omnivision OVM7620 Datasheet]] *[[media:C3188A.pdf|C3188A Camera Module]] *[[media:C3188A SCHEMATIC.pdf|C3188A Camera Module Schematic]] *[[media:OVM7690.pdf|OmniVision OVM7690]] *[[media:Cy7c68013a 8-2.pdf|Cypress CY7C68013A]] *[[media:Cp2102-1.pdf|Silicon Labs CP2102]] *[[media:Xps usb2 device.pdf|Xilinx USB Core]] *[[media:DS FT2232D.pdf|FTDI FT2232D]] *[[media:Dlp2232m-v15-ds.pdf|DLP 2232M-G]] *[[media:DS FT245BM.pdf|FTDI FT245BM]] *[[media:Dlp-usb245mv15.pdf|DLP USB245M]] *[[media:Pci 23.pdf|PCI 2.3 Specification]] *[[media:Ds099.pdf|Xilinx Spartan 3 FPGA]] *[[media:Ds557.pdf|Xilinx Spartan 3AN FPGA]] *[[media:IGLOO HB.pdf|Actel Igloo FPGA]] *[[media:TDS 340A Manual.pdf|TDS 340A Manual]] *[[media:S3BOARD-brochure.pdf|Digilent S3 Board Brochure]] *[[media:S3BOARD-rm.pdf|Digilent S3 Board User's Guide]] *[[media:S3BOARD-sch.pdf|Digilent S3 Board Schematic]] *[[media:S3 Adapter Schematic.pdf|S3 Adapter Schematic]] *[[media:ExpressPCB Layout.bmp|S3 Adapter Layout]] *[[media:Blk mem gen ds512.pdf|Xilinx Block Memory Datasheet]] *[[media:PI6C4511.pdf|PI6C4511]] *[[media:NB3L553-D.pdf|NB3L553]] 2d438615680d81a6627177b52f7df7684bba8ff1 0 5 209 103 2010-02-04T18:48:46Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m. Lopata 302 Mid-term Exam: February 16, 2010, during class. Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 7e11bc11888c0690938f363741d44f15daae19f5 274 209 2010-04-05T15:58:39Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m. Lopata 302 Mid-term Exam: February 16, 2010, during class. Final Exam: May 11, 2010, 1-3 p.m. Paper Due: April 30, 2010, 3 p.m. Project Presentations: April 29, 2010, during class. Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. db7edb4c8d4fd162968478026a4a51fb7a4a0d31 6 100 227 2010-02-11T14:00:11Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 101 228 2010-02-11T14:00:23Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 36 264 112 2010-02-18T15:57:01Z Wdr 2 wikitext text/x-wiki *[[media:Spring_10_Exam_1_Solution.pdf‎|Exam #1 Solution]] e9ad0f47745dc26f19412a11115724165fd29951 267 264 2010-02-18T19:02:29Z Wdr 2 wikitext text/x-wiki *[[media:Spring_10_Exam_1_Solution.pdf‎|Exam #1 Solution]] *[[media:Stick.pdf‎ |Exam #1 Results]] 9cbb72b95e13ac89d46d14769742e9d0df648d00 0 30 275 272 2010-04-06T17:09:14Z Wdr 2 wikitext text/x-wiki *[[media:MCLK_Waveform.BMP|Master Camera Clock Waveform]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Datasheet.pdf|Loop-Back FPGA Datasheet]] *[[media:Adapter Schematic.pdf |Final Adapter Schematic]] *[[media:Final PCB.bmp|Final PCB]] *[[media:Adapter Block Diagram.pdf|Adapter Block Diagram (For HW #3)]] *[[media:Final Adapter Block Diagram.pdf|Final Adapter Block Diagram]] *[[media:Stereo_Vision.pdf|Stereo Vision]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] *[[media:sn74ls04.psf|74LS04]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] b0f475125c0da29728daa82ed9ec216fe205a0af 277 275 2010-04-06T17:10:13Z Wdr 2 wikitext text/x-wiki *[[media:MCLK_Waveform.BMP|Master Camera Clock Waveform]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Datasheet.pdf|Loop-Back FPGA Datasheet]] *[[media:Adapter Schematic.pdf |Final Adapter Schematic]] *[[media:Final PCB.bmp|Final PCB]] *[[media:Adapter Block Diagram.pdf|Adapter Block Diagram (For HW #3)]] *[[media:Final Adapter Block Diagram.pdf|Final Adapter Block Diagram]] *[[media:Stereo_Vision.pdf|Stereo Vision]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] *[[media:Sn74ls04.pdf‎|74LS04]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] 276f71ebafd481edf1ca92098380405785470ef9 282 277 2010-11-16T19:10:53Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] 61d8f5fed5ed1d411b9dfb005b38c6cb992821fd 289 282 2011-01-18T16:12:07Z Wdr 2 wikitext text/x-wiki [http://www.cnbc.com/id/15840232?video=1122557312&play=1| USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd| Commercial Fetal Doppler Unit] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] 8e65cc6b6545491f97195eaac48eb2f4bb8f8a20 290 289 2011-01-18T16:12:36Z Wdr 2 wikitext text/x-wiki *[http://www.cnbc.com/id/15840232?video=1122557312&play=1| USB Ultrasound Probe] *[http://www.storkradio.com/dopplers-digital.php#srdd| Commercial Fetal Doppler Unit] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] e1fc889362e9f94f9c74e9562d54511a73f17ab4 291 290 2011-01-18T16:13:37Z Wdr 2 wikitext text/x-wiki [http://www.cnbc.com/id/15840232?video=1122557312&play=1| USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd| Commercial Fetal Doppler Unit] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] 8e65cc6b6545491f97195eaac48eb2f4bb8f8a20 292 291 2011-01-18T16:14:06Z Wdr 2 wikitext text/x-wiki Links: [http://www.cnbc.com/id/15840232?video=1122557312&play=1| USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd| Commercial Fetal Doppler Unit] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] 3617d6aeb2cb12adb3a44a55b9e1cc80ef14bb25 293 292 2011-01-18T16:14:28Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1| USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd| Commercial Fetal Doppler Unit] 81d680bce1e1cf48d3e1e1f7126d61d6a4a6866e 294 293 2011-01-18T16:15:36Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics| ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1| USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd| Commercial Fetal Doppler Unit] 015076831233479f593700f614702e7c2a82b02e 295 294 2011-01-18T16:16:13Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics | ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 | USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd | Commercial Fetal Doppler Unit] e40c4d3c05366312a1b969c7d56ac1a9c019fbd4 296 295 2011-01-18T16:16:32Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] 4a8d20215e0c188196109eaff70bfbef880acec9 297 296 2011-01-18T16:19:57Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] e8bfeda53bd0dcfdc2bb84cdb4196f9764ef9e02 298 297 2011-01-18T16:20:09Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] fffc1152869959e9e12ab2859a9efda4cbb377e1 299 298 2011-01-18T16:25:45Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] [http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2595531/pdf/yjbm00139-0045.pdf Pulsed Doppler Fundamentals] 040c1f80c25df018c14f37dd0f33bd43b8d74a60 335 299 2011-02-15T18:52:04Z Wdr 2 wikitext text/x-wiki *[[media:TUTORIAL.pdf|Visual Studio 2008 Command Line Compiler Tutorial]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] [http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2595531/pdf/yjbm00139-0045.pdf Pulsed Doppler Fundamentals] 99be33f1af336368cdd48fc9608c3b1d16e4dba9 0 5 278 274 2010-04-27T18:10:27Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m. Lopata 302 Mid-term Exam: February 16, 2010, during class. Final Exam: May 11, 2010, 1-3 p.m. Paper Due: May 4, 2010, 3 p.m. Project Presentations: April 29, 2010, during class. Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 959ebc1232ed4969bb39f880659264e7327a76c6 280 278 2010-11-16T19:09:21Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Room TBD Mid-term Exam: TBD Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. b748fd5fc72e496651ba5650ab218f75a5faf323 288 280 2011-01-18T16:10:07Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462 Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Lopata Hall Room 103 Mid-term Exam: TBD Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. ebe09b635fc581551b130af9607ca8f46adbd32d 300 288 2011-01-18T19:12:22Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462/index.php/Main_Page Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Lopata Hall Room 103 Mid-term Exam: TBD Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 5cb42471e4b3608ba992ef0ff5a72f5974d80538 340 300 2011-02-17T17:16:14Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-2:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse462/index.php/Main_Page Text: NA (You should have access to a VHDL reference.) Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Lopata Hall Room 103 Mid-term Exam: March 8th, 2011 Final Exam: TBD Paper Due: TBD Project Presentations: TBD Grading: Two exams, 30% each. Project: 30%. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 47d1815c73a3111d00db866364698f52c4ae2462 0 35 279 241 2010-11-16T18:51:02Z Wdr 2 wikitext text/x-wiki *[[media:HW1.pdf|Homework #1]] 05be29cab9a9675c2e358477f8e94e4beb0e25f8 314 279 2011-02-03T15:42:12Z Wdr 2 wikitext text/x-wiki *[[media:HW1.pdf|Homework #1]] *[[media:HW1_Solution.pdf|Homework #1 Solution]] *[[media:HW2.pdf|Homework #2]] 2eb4b719f6097ce3a841cae8bfc0c88d001f1244 332 314 2011-02-10T21:01:51Z Wdr 2 wikitext text/x-wiki *[[media:HW1.pdf|Homework #1]] *[[media:HW1_Solution.pdf|Homework #1 Solution]] *[[media:HW2.pdf|Homework #2]] *[[media:HW3.pdf|Homework #3]] f86ba3ec339139ea15c7c8b5faf17eade2c91d83 336 332 2011-02-17T17:14:39Z Wdr 2 wikitext text/x-wiki *[[media:HW1.pdf|Homework #1]] *[[media:HW1_Solution.pdf|Homework #1 Solution]] *[[media:HW2.pdf|Homework #2]] *[[media:HW3.pdf|Homework #3]] *[[media:HW3_Solution.pdf|Homework #3 Solution]] *[[media:HW4.pdf|Homework #4]] *[[media:HW5.pdf|Homework #5]] 78eeb452ef4f3e43a3384cabf5a6c09ab9a98db2 0 1 281 115 2010-11-16T19:09:41Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE462M''' '''COMPUTER SYSTEM DESIGN''' </font> <font size=3> '''Spring 2011''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' ---- Capstone Computer Engineering Design Course. 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Diagram]] *[[media:Adapter_Schematic.pdf|USB Adapter Schematic]] *[[media:LTC1799.pdf|LTC1799]] *[[media:MCP1700.pdf|MCP1700]] *[[media:AP2141_51.pdf|AP2141]] *[[media:Ds312.pdf|Xilinx Spartan 3E FPGA]] *[[media:Sn74ls04.pdf|74LS04 Inverter]] *[[media:MD1210.pdf|Supertex MD1210]] *[[media:TC6320.pdf|Supertex TC6320]] *[[media:MIC4426.pdf|Micrel 4426/4427/4428]] *[[media:MD0100.pdf|Supertex MD0100]] *[[media:MD0105.pdf|Supertex MD0105]] *[[media:MD0100DB1.pdf|Supertex MD0100DB1 Demo Board]] *[[media:Fifo_generator_ds317.pdf|Xilinx FIFO Generator Datasheet]] *[[media:Fifo_generator_ug175.pdf|Xilinx FIFO Generator User's Guide]] 6de2c051659f2f11967b0c6cf55a337a3a2c12f3 8 2 286 168 2010-11-16T19:14:01Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://www.tyzx.com | TYZX, Inc. ** http://www.ftdichip.com | Future Technology Devices International Limited ** http://www.cypress.com | Cypress ** http://www.dlpdesign.com | DLP Design ** http://www.usb.org | USB Implementers Forum ** http://1394ta.org | 1394 Trade Association ** http://www.pcisig.org | PCI Special Interest Group * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 966b8f3cf0b0838bb7f25268b0f1c2e0d29a0ca9 287 286 2010-11-16T19:14:19Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://www.ftdichip.com | Future Technology Devices International Limited ** http://www.cypress.com | Cypress ** http://www.dlpdesign.com | DLP Design ** http://www.usb.org | USB Implementers Forum ** http://1394ta.org | 1394 Trade Association ** http://www.pcisig.org | PCI Special Interest Group * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 82387e026716c969c04b1114e1789a502b8cbb79 0 46 366 364 2011-03-08T18:50:50Z Wdr 2 wikitext text/x-wiki *[[media:fakebackend2.vhd|fakebackend2.vhd file]] *[[media:fakebackend.vhd|fakebackend.vhd file]] *[[media:my_rom.txt|my_rom.coe file (change the extension to .coe)]] *[[media:Groups.pdf|Project Groups]] *[[media:SPRING_2011_PROJECT_ASSIGNMENT.pdf‎|Project Assignment]] *[[meida:SPRING_2011_PAPER.pdf‎|Project Paper]] *[[media:Gantt.pds|Project Gantt Chart]] 130159526370fbb8e3483a7ebafa3b245676eeb5 367 366 2011-03-08T18:51:40Z Wdr 2 wikitext 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Wdr 2 wikitext text/x-wiki *[[media:Digilent Spartan 3E Starter Board Schematic.pdf|Digilent Spartan 3E Starter Board]] d698a6355c1352f0875cb7fcb1c1ecad0b0af1c1 0 30 397 335 2011-04-26T15:00:56Z Wdr 2 wikitext text/x-wiki *[[media:UCF.pdf|Initial UCF File]] *[[media:TUTORIAL.pdf|Visual Studio 2008 Command Line Compiler Tutorial]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] [http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2595531/pdf/yjbm00139-0045.pdf Pulsed Doppler Fundamentals] bde665d5682a03ab6cff862dfc498e1c9e752364 398 397 2011-04-26T15:03:04Z Wdr 2 wikitext text/x-wiki *[[media:UCF.pdf|Initial UCF File]] *[[media:TUTORIAL.pdf|Visual Studio 2008 Command Line Compiler Tutorial]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.xilinx.com/itp/xilinx4/data/docs/cgd/types2.html Xilinx Timing Model] [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] [http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2595531/pdf/yjbm00139-0045.pdf Pulsed Doppler Fundamentals] 2b00e4a0d28e3eecbe7e97a64cb880dd7b3f94ac 399 398 2011-04-26T15:26:44Z Wdr 2 wikitext text/x-wiki *[[media:UCF.pdf|Initial UCF File]] *[[media:TUTORIAL.pdf|Visual Studio 2008 Command Line Compiler Tutorial]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] *[[media:Metastability 1.pdf|Metastability 1]] *[[media:Metastability 2.pdf|Metastability 2]] *[[media:ieee_codeofethics.pdf|IEEE Code of Ethics]] *[[media:Employment Contract - Clean.pdf|Employment Contract]] Links: [http://www.xilinx.com/itp/xilinx4/data/docs/cgd/types2.html Xilinx Timing Model] [http://www.1-core.com/library/digital/fpga-design-tutorial/implementation_xilinx.shtml Xilinx Tool Flow Article by Core Technologies] [http://www.acm.org/about/code-of-ethics?searchterm=code+of+ethics ACM Code of Ethics] [http://www.cnbc.com/id/15840232?video=1122557312&play=1 USB Ultrasound Probe] [http://www.storkradio.com/dopplers-digital.php#srdd Commercial Fetal Doppler Unit] [http://www.bellybeats.com/index.php?cPath=2&osCsid=74984618a49aa418e3202b24a3366f98 Commercial Fetal Doppler Unit] [http://www.ncbi.nlm.nih.gov/pmc/articles/PMC2595531/pdf/yjbm00139-0045.pdf Pulsed Doppler Fundamentals] 59791c2b68a9b52116a9b06295d2521599275079 404 399 2012-01-18T16:53:57Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:EVERYTHING YOU ALWAYS WANTED.PDF|VHDL Lecture]] 013aed39ed03538a744bdb72d9d5d09d60c15414 405 404 2012-01-18T16:54:21Z Wdr 2 wikitext text/x-wiki *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 0d7d838f7c4d93ea8f1eb437ffe2887a81aea4d2 417 405 2012-01-18T19:45:32Z Wdr 2 wikitext text/x-wiki *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Output]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 3658ca50ca804339b884970760293a3f899f6d94 420 417 2012-01-18T20:19:18Z Wdr 2 wikitext text/x-wiki *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:Metastability 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Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 123e204495e22b5e43f1fe8599f9028c6c910049 0 1 400 281 2012-01-18T16:49:08Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2012''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday, 1:00 - 2:30 p.m.''' ---- Prerequisites: CSE 260M 459922db8492bedb4b1d41b7e281ab0cfca3ea12 0 5 401 340 2012-01-18T16:51:37Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460T/index.php/Main_Page Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Earth and Planetary Sciences 102 Mid-term Exams: TBD Final Exam: TBD Grading: Four exams, 22.5% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. a71f561965f43715330512df8a0f8c134d33972b 402 401 2012-01-18T16:52:06Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Earth and Planetary Sciences 102 Mid-term Exams: TBD Final Exam: TBD Grading: Four exams, 22.5% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due one week after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. 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Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 808b317480b7ce276bd009ea428c627d4bf1affb 422 421 2012-01-19T16:03:05Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Earth and Planetary Sciences 102 Mid-term Exam I: TBD Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 30% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 1ce81aca3cf96ad0ac976b102586b7357187e155 0 6 403 16 2012-01-18T16:52:44Z Wdr 2 Replaced content with '# TBD ## TBD ## TBD # TBD' wikitext text/x-wiki # TBD ## TBD ## TBD # TBD 56580c987a54a82787c0a3e093a8955f3a1bca08 0 35 406 336 2012-01-18T16:54:44Z Wdr 2 wikitext text/x-wiki *[[media:HW1.pdf|Homework #1]] 05be29cab9a9675c2e358477f8e94e4beb0e25f8 424 406 2012-01-19T16:06:01Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] d4a2965f0851f44756236e7a52dae560b5993a3d 432 424 2012-01-24T15:15:50Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] e2fff0dac91b81f41ee367a38f3f18f13e12a91d 8 2 410 287 2012-01-18T16:57:08Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://www.usb.org | USB Implementers Forum * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES d8ac6d899c3761b4c5e059ce191c6590a0806bfa 6 159 412 2012-01-18T19:40:25Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 160 418 2012-01-18T19:46:01Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 161 419 2012-01-18T19:46:10Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 163 427 2012-01-19T16:23:36Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 431 427 2012-01-19T16:26:11Z Wdr 2 uploaded a new version of "[[File:CyclicExample.txt]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 164 428 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*[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] e01455e49b175f5776a024eccb5cb6ede9aa5dd7 444 442 2012-01-26T15:23:23Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 2c4f163adfabc63f2b76efc256857c5d9efd7c2b 446 444 2012-01-26T15:24:09Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|Synthesized RTL Schematic]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] ff403fc519177cbb02f2c002b840b54b82052e12 448 446 2012-01-26T15:25:09Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|Xilinx Spartan 6 Technology Map Schematic]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] a06ec88f71bfff845b6980afdb42c211e7a1f006 449 448 2012-01-26T15:25:50Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|Xilinx Spartan 6 Technology Map Schematic]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 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Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:P145-cong.pdf|Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 19c5f0b1ff8909d592c3f859bd90246e27bcd4be 456 455 2012-01-26T15:35:15Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] e08cb93ac9088fb4ae3251ec86d307cc03f19614 462 456 2012-01-30T19:16:51Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 8c360a55f7458a538b73c69975afdd8d6a9b6fa8 463 462 2012-01-30T19:19:34Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 1df8549e3f44031cdf163248c197a776887904ab 475 463 2012-01-31T16:51:42Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] f9b6c8a2640829aa9b2069a7fc50189698d2ed93 492 475 2012-02-02T21:20:51Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 9bda804a78c2b7c5ef0ac62f6be64263b6b802a0 495 492 2012-02-02T21:24:31Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 003979a4eb416352c419965de88b785000854753 497 495 2012-02-02T21:33:53Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] eccd5bcefd95fa4fcf89127946a93aaf386161eb 6 168 443 2012-01-26T15:22:35Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 169 445 2012-01-26T15:23:38Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 170 447 2012-01-26T15:24:28Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 171 450 2012-01-26T15:26:02Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 172 451 2012-01-26T15:26:10Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 173 452 2012-01-26T15:26:20Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 174 454 2012-01-26T15:29:33Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 8 2 461 410 2012-01-30T18:36:14Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://www.arl.wustl.edu/~lockwood/class/cse460/ | Lockwood Course Slides ** http://classes.engineering.wustl.edu/cse460/index.php/Main_Page | Zar Course Slides ** http://www.usb.org | USB Implementers Forum * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 3417a95a9c795154986f341ec27a098d2ae5089a 6 177 464 2012-01-30T19:20:45Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 178 465 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 179 466 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 180 467 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 181 468 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 182 469 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 183 470 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 184 471 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 185 472 2012-01-30T19:20:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 186 473 2012-01-31T16:50:44Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 187 474 2012-01-31T16:50:56Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 190 481 2012-02-02T14:52:43Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 46 482 416 2012-02-02T14:53:22Z Wdr 2 wikitext text/x-wiki *[[media:Espresso.zip|Espresso for DOS]] *[[media:Edwin_Robbins.jpg|View from Edwin Robbins' Window]] 88930322b07dcfab7b2bf3be7d76b186703432e8 0 6 483 403 2012-02-02T14:57:42Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # K-LUT Mapping 8d3ed6e68c95558674e571c40975701adf3820bc 484 483 2012-02-02T14:58:35Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-LUTs 43c474e1f4937d51a5683398bf288009e8733699 485 484 2012-02-02T15:03:09Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-Input LUTs b6a7cd0e27935579aeb8fa2a61cdb40c4270a9fb 0 5 488 422 2012-02-02T16:40:30Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Earth and Planetary Sciences 102 Mid-term Exam I: February 14, 2012 Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 30% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. fa54b9ce9ec3e7a5843ea677203ec6bb598f0093 6 192 491 2012-02-02T21:19:55Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 193 493 2012-02-02T21:21:03Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 194 494 2012-02-02T21:23:23Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 195 496 2012-02-02T21:24:39Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 498 497 2012-02-02T21:34:02Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 90ab854666e84199e089a48047abef4dc034ef30 499 498 2012-02-02T21:39:52Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] f30928c46d45397e76e0c6452eaadf3b11ee0ba8 500 499 2012-02-02T21:43:17Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 9fd25106daa3c8a2b4a683324e98305136e81b1c 501 500 2012-02-02T21:44:19Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 248c6580f9f4081574fae6b99f0f4532b7f68412 502 501 2012-02-02T21:49:12Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] ee3092f0e29e9feb9958de9503fb01c1d18e0ef2 503 502 2012-02-02T21:49:25Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 3d7ca8189cf616a07084dc312a413d4b534e96fd 504 503 2012-02-03T19:17:12Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] dce085baa8a7922cf896aa28b6f35ba95a87e5c2 508 504 2012-02-03T19:19:15Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (3121 LUTS)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic (87 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] c399eb6bc1746fcc5e0aeefb78ffa94f0834a14c 509 508 2012-02-03T19:20:29Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (3121 LUTS)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic (87 LUTs)]] *[[media:Example11.vhd|VHDL Example 10]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] be7a8d79da0602f6823ed404a2aee2ecaf92769e 510 509 2012-02-03T19:26:25Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example8Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic (87 LUTs)]] *[[media:Example11.vhd|VHDL Example 10]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] fa8d863990c337081f73a40186d1590534c96dbb 511 510 2012-02-03T19:27:09Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic (87 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 09e4022da0c9f6cdf2b46b2ed7963bc5551b2c74 515 511 2012-02-05T17:46:17Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] dd08a6556552ec4c7b1fb5ef6a2af052b7cb169b 516 515 2012-02-05T17:50:29Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] ee4d99b0031eafab7585469cebd6c662ce997b7c 518 516 2012-02-05T17:56:06Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 78a780bf00938fb9d7e59eb47e020f6a2c94e97c 519 518 2012-02-05T17:56:38Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 64f55ab62a41b26166b9083e91a05625c0718bd5 520 519 2012-02-05T17:57:00Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (81 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] b296f2233014778373d1047a13ba8e4b5e48aba5 524 520 2012-02-05T18:09:38Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 236e1822b1f03cbd73547f190532b288a3895eab 525 524 2012-02-05T18:10:02Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 97d0611aa632b819455ec790d0a39688a95465df 526 525 2012-02-05T18:48:33Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 98cc28a1a258d76e4a32621b04364dbec2770b70 528 526 2012-02-09T16:33:07Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Bit_Zero_Optimal_LUTS.pdf|Bit Zero Optimal LUTS]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 94402434db18b074fc189d25d5030357f28bce5a 530 528 2012-02-09T16:33:41Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 81581fd8a32891b0dfc0f657560345b5cc906a06 532 530 2012-02-09T18:51:54Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 136be1c1e6cbe2953115de098501789e055fd685 536 532 2012-02-10T20:43:27Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 12.147 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 787187517328f710bb6fc7e6fbebb03019ecb7c3 537 536 2012-02-10T20:54:04Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 12.147 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] ffa2c2264324e97f4f9ee54ae2fa8e7e30575ccd 538 537 2012-02-13T17:04:29Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 67df8413c4426e4ec32b0b5ef5ecf397d8a28c72 539 538 2012-02-13T18:13:54Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 3f8218936061350ea4b20b504b7efd7c2d028d75 543 539 2012-02-13T18:19:57Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] bc472b765430d8caab1127842faecf954103bed8 545 543 2012-02-13T18:21:04Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 240990c1be470e4716d83edcb369f94aad60a7a9 546 545 2012-02-13T18:22:28Z Wdr 2 wikitext text/x-wiki #Logic Minimization ##*[[media:Standard_Cell.JPG|Standard Cell Example]] ##*[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] bfab4a2914439ab1a1aac178a5393de4cf2bb0cd 547 546 2012-02-13T18:22:54Z Wdr 2 wikitext text/x-wiki #Logic Minimization *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 07687690ed80e6027c5c919d2b544b25585c6cfa 548 547 2012-02-13T18:23:08Z Wdr 2 wikitext text/x-wiki *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 240990c1be470e4716d83edcb369f94aad60a7a9 549 548 2012-02-13T18:23:47Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] da9c434e9d643f71fcbb8f04aec6c39b6496bf16 6 196 505 2012-02-03T19:17:29Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 197 506 2012-02-03T19:17:49Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 198 507 2012-02-03T19:17:56Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 199 512 2012-02-03T19:29:11Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 522 512 2012-02-05T18:06:45Z Wdr 2 uploaded a new version of "[[File:Example11.vhd]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 200 513 2012-02-03T19:29:19Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 523 513 2012-02-05T18:08:31Z Wdr 2 uploaded a new version of "[[File:Example11Technology.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 201 514 2012-02-03T19:29:34Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 202 517 2012-02-05T17:54:39Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 203 521 2012-02-05T18:06:13Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 204 527 2012-02-05T18:49:02Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 205 529 2012-02-09T16:33:23Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 206 531 2012-02-09T18:51:17Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 533 486 2012-02-09T18:54:26Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] e83728f06c844d977d49c37b027e2eef5e2feb32 6 208 540 2012-02-13T18:14:14Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 541 540 2012-02-13T18:15:41Z Wdr 2 uploaded a new version of "[[File:Figure7dot4.vhd]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 209 542 2012-02-13T18:19:18Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 210 544 2012-02-13T18:20:13Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 550 549 2012-02-13T18:24:36Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 9fc5ea65f927e8a4f2861a23c04f2a6f2b170ada 551 550 2012-02-13T18:25:14Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 560ec3e95c3ddb72af2377ab2234371c1f64f49a 552 551 2012-02-13T19:04:11Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] e1dded860b577a2796a9fe3279ca62e4b97e3cd7 557 552 2012-02-13T19:13:33Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 2764fde65bd137a13b613d5ea7f85c10c8760218 558 557 2012-02-13T19:15:22Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 0196fac7917989549d0b75a986095a69f25941fc 561 558 2012-02-13T19:25:37Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 47b1d10a2b9d9f38fe0fddc1901d6deae542eb35 568 561 2012-02-16T16:15:34Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] ec6d94afa24f319272a9e2e09aa519e55290d84c 570 568 2012-02-16T16:16:35Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 6e16e2d8b96dad8d00352e67cef0e03a1f1bce37 572 570 2012-02-16T16:19:03Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 4b7a8891b4212eae8d78ce2ecf7e345d3614ef60 573 572 2012-02-23T15:29:07Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 8abf84e128fa49ed4f2221c1b807d9db4750b3b5 580 573 2012-02-23T20:25:43Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 7a2360348b3e391e8a40752e2529ffb9b9e24f14 581 580 2012-02-28T15:54:45Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification by Implication Tables]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 18870d4f8e1d17cd34d54fcd38b156f35c4ea6af 590 581 2012-02-28T18:22:00Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 690b0b49d99b96ce4f0757904866f1e7db89f103 591 590 2012-03-01T15:54:36Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] d321e9d3f41195e3d7ff619f6af210c38da03cd1 592 591 2012-03-01T15:54:58Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 0f37c24fd74b374c84ee7225d05760f8f8ea21e4 597 592 2012-03-05T19:33:20Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 6cb7ad1bc431647a7a5ae08400446a94cd616e58 599 597 2012-03-06T16:22:53Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 0e559da3d529962f8094ba898ff9c94aba1acff6 609 599 2012-03-19T19:16:12Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] d5da36fdaed1e1376c18673eb11802d513bb04bf 6 211 553 2012-02-13T19:04:30Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 212 554 2012-02-13T19:04:40Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 555 554 2012-02-13T19:10:22Z Wdr 2 uploaded a new version of "[[File:Figure7dot4v3.vhd]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 213 556 2012-02-13T19:12:50Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 214 559 2012-02-13T19:24:35Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 215 560 2012-02-13T19:24:43Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 36 563 376 2012-02-16T15:02:28Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Solution.pdf‎|Exam #1 Solution]] 18578671f0ca9f5dd01c07740ac7c0e50e1b5c10 566 563 2012-02-16T15:04:24Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Solution.pdf‎|Exam #1 Solution]] *[[media:Exam_1_Results.pdf|Exam #1 Results]] a5c2dceb50a161b3411b6363364571dceefc320d 578 566 2012-02-23T15:33:01Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Results.pdf|Exam #1 Results]] d53073b8f850f4631cc856f82a1dc4953094119a 6 218 567 2012-02-16T16:14:56Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 219 569 2012-02-16T16:15:57Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 220 571 2012-02-16T16:18:01Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 221 574 2012-02-23T15:29:23Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 576 533 2012-02-23T15:31:45Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] 25bae3e0ca942fa6534dc199d789a84207e9fd9f 587 576 2012-02-28T18:16:30Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_6.pdf|Homework #6 Partial]] dd4a05ec45b09d97ea7a813f690fedbf5c8a3c47 594 587 2012-03-01T15:56:24Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Partial]] 116ce9b97c172d1c83e5367eac0565d34c7703d0 604 594 2012-03-08T17:41:48Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] ba0e680f9ded6b848d444213a0445ea98f500d85 606 604 2012-03-08T19:00:51Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7]] d2af4ab22b791175cf5f0def01e543687991e257 613 606 2012-03-22T15:16:38Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8]] 47321ed15a28bb80287cc96c3a2f68bb858e369a 6 223 579 2012-02-23T20:24:53Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 224 582 2012-02-28T15:54:59Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 583 582 2012-02-28T16:05:59Z Wdr 2 uploaded a new version of "[[File:Simplification by Implication Tables.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 6 584 485 2012-02-28T16:58:09Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-Input LUTs # Sequential Systems ## State Minimization ### Partition Tables ### Implication Tables 917b252a9f2cc1bf918c2a6fd027857f992da1c7 588 584 2012-02-28T18:20:48Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-Input LUTs # Sequential Systems ## State Minimization of Completely Specified Machines ### Partition Tables ### Implication Tables ## State Minimization of Incompletely Specified Machines ### Partition Tables c472e1ddc8dbe64787dcf5d28b90ec3bfc62cd1a 589 588 2012-02-28T18:21:01Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-Input LUTs # Sequential Systems ## State Minimization of Completely Specified Machines ### Partition Tables ### Implication Tables ## State Minimization of Incompletely Specified Machines ### Implication Tables 8d2485db644356ec65d1ceb161ba89b6553c876d 0 5 585 488 2012-02-28T16:58:55Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Earth and Planetary Sciences 102 Mid-term Exam I: February 14, 2012 Mid-term Exam II: TBD Final Exam: April 26, 2012 Grading: Three exams, 30% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. a413e1648b748d33f63fb7d688f8504b0ea81881 6 227 596 2012-03-05T19:32:24Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 228 598 2012-03-06T16:22:08Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 600 598 2012-03-06T16:23:40Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 601 600 2012-03-08T17:33:50Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 602 601 2012-03-08T17:40:24Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 608 602 2012-03-19T19:12:59Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 228 617 608 2012-03-22T17:32:24Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 621 617 2012-03-27T16:04:21Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 619 613 2012-03-27T16:01:15Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] 3ea6a01f92511fe543a7eebffe403724f2f5da26 655 619 2012-04-10T17:44:00Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9]] 317056b719ef658ca6f576d1f07838c515e21576 658 655 2012-04-12T17:45:07Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9]] *[[media:Homework_10.pdf|Homework #10]] fb7eb289ec9f739bc8e5f25d279c5d133509e8a9 663 658 2012-04-17T16:15:33Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_K-Map.pdf|Homework #3 K-Map]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] 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*[[media:Homework_1.pdf|Homework #1]] d4a2965f0851f44756236e7a52dae560b5993a3d 0 30 624 609 2012-04-03T16:54:24Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:D_flip_flop.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] fbb01b32bafe776a446fdbb664c3131adcf40cf6 626 624 2012-04-03T16:55:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] efb79866971685a3d4a5a5742073973d293d09ff 628 626 2012-04-03T16:56:04Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] f33dbde3151cd8cf0bcc05e5582651032477bfc1 630 628 2012-04-03T17:03:28Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 3ce93558bf197e78212c886577f7da41012c4ae1 635 630 2012-04-03T17:28:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description *[[media:norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 85d7dcdc2c95e029ff9646abd39adcf3441c2373 637 635 2012-04-03T17:28:48Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 5c9e9622401bbfaf17741b68aa3295226b0205e8 638 637 2012-04-03T17:29:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 2b225c4e55377b2015a7c8deccfece3deed73407 640 638 2012-04-03T17:33:55Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 5349dcde1047365af1840fe16b19e8c012f32e2d 643 640 2012-04-03T17:42:52Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] b817b3b538f10f39c13b015e5be6a1df44f8ec63 644 643 2012-04-03T17:43:00Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 6c6bea8e20cd18f357186e8b20b7f6a5794eee1c 646 644 2012-04-03T18:00:19Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] 10219a0731a0ec9dcd650c9e81d84b67b7e39824 648 646 2012-04-05T17:51:28Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] bffe16f269e2cbfba5891945bf3036b240e7b65f 651 648 2012-04-06T17:27:24Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] eecf1747fd24229dae798e06144b5fdeba944db7 653 651 2012-04-06T17:28:21Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] d1199ceba7484f1e5c97a11a65a4c1b1dcc3c402 660 653 2012-04-17T15:45:01Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|Kohavi on State Assignment]] c2e3aa1f25e1f391caa43b36a8a207a3b09b01e4 661 660 2012-04-17T15:46:06Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 759c4adf31f7118cdf4d51af5be6b69d7f10202a 673 661 2012-04-19T17:27:38Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 47088701379c65337a5e829d1775f8d6af04afd5 6 235 625 2012-04-03T16:54:44Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 236 627 2012-04-03T16:55:28Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 641 627 2012-04-03T17:42:07Z Wdr 2 uploaded a new version of "[[File:Dflopsim.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 237 629 2012-04-03T17:02:53Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 36 632 578 2012-04-03T17:05:57Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Results.pdf|Exam #1 Results]] *[[media:Exam_2_Solution.pdf|Exam #2 Solution]] *[[media:Exam_2_Results.pdf|Exam #2 Results]] 360e9acdfc14a293a1fe0d06c7f6ba2c96af4067 681 632 2013-12-17T17:00:31Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Results.pdf|Exam #1 Results]] d53073b8f850f4631cc856f82a1dc4953094119a 6 240 634 2012-04-03T17:27:09Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 241 636 2012-04-03T17:28:18Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 242 639 2012-04-03T17:33:27Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 243 642 2012-04-03T17:42:17Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 244 645 2012-04-03T17:59:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 245 647 2012-04-05T17:50:45Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 649 647 2012-04-05T17:52:11Z Wdr 2 uploaded a new version of "[[File:Metastability Lecture.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 246 650 2012-04-06T17:26:48Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 247 652 2012-04-06T17:27:44Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 250 659 2012-04-17T15:44:27Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 254 672 2012-04-19T17:27:03Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 5 679 585 2012-04-25T18:15:26Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Monday and Wednesday, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 1:00-2:30 a.m., Earth and Planetary Sciences 102 Mid-term Exam I: February 14, 2012 Mid-term Exam II: March 29, 2012 Final Exam: April 26, 2012 Grading: Three exams, 30% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 07f016f1d6da912db40fe69e453feeb3f1743078 0 1 682 400 2014-01-10T03:28:27Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2014" '''William D. Richard, Ph.D.''' ---- '''Monday/Wednesday 11:30 - 1:00 p.m.''' ---- Prerequisites: CSE 260M 07216fc93d616839def8464bbc4a81c6d2f13b5d 683 682 2014-01-10T03:29:06Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2014'" '''William D. Richard, Ph.D.''' ---- '''Monday/Wednesday 11:30 - 1:00 p.m.''' ---- Prerequisites: CSE 260M 5e806270505b96316e22fe1bea249ef3ff5075cb 684 683 2014-01-10T03:29:37Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2014"' '''William D. Richard, Ph.D.''' ---- '''Monday/Wednesday 11:30 - 1:00 p.m.''' ---- Prerequisites: CSE 260M ed83d6ec875a58bc8f0df83ae20c26ff708e5cd3 685 684 2014-01-10T03:30:36Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2014.''' '''William D. Richard, Ph.D.''' ---- '''Monday/Wednesday 11:30 - 1:00 p.m.''' ---- Prerequisites: CSE 260M 58e61b073c5ab1a4cff2dd4f1e7800a1105aebbf 686 685 2014-01-10T03:30:53Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2014''' '''William D. Richard, Ph.D.''' ---- '''Monday/Wednesday 11:30 - 1:00 p.m.''' ---- Prerequisites: CSE 260M 53f1bc688dea937fb2f0c6253042f2b9f1c26208 0 5 687 679 2014-01-10T03:33:49Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Tuesdays and Thursdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Mondays and Wednesdays, 11:30 a.m. - 1:00 p.m., Lab Sciences ? Mid-term Exam I: TBD Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 30% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. c52e5c57b7e31440055d810777f29ce295a5c2c4 688 687 2014-01-10T03:36:21Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Tuesdays and Thursdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Mondays and Wednesdays, 11:30 a.m. - 1:00 p.m., Lab Sciences 250 Mid-term Exam I: TBD Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 30% each. Homework/quizzes are 10%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. 04eb91c878f9211246c2eb5bfac72c72101faa6d 689 688 2014-01-13T01:33:14Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Tuesdays and Thursdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Mondays and Wednesdays, 11:30 a.m. - 1:00 p.m., Lab Sciences 250 Mid-term Exam I: TBD Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 33.33% each. Homework/quizzes are 0%. Homework: Homework will be assigned weekly. It will be due the class period after it is assigned. Homework will be turned in at the start of class on the due date. No late homework will be accepted. Homework should be done on an individual basis but you may confer with your friends, course consultants, graders, etc. d58ee6f379e0f694317d0889ad082f2dd6435ede 690 689 2014-01-13T01:45:57Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Tuesdays and Thursdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Mondays and Wednesdays, 11:30 a.m. - 1:00 p.m., Lab Sciences 250 Mid-term Exam I: TBD Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 33.33% each. Homework/quizzes are 0%. Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded by the instructor and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity. 9b90699623bc3bdf7276caa5492b5026555a63e2 0 6 691 589 2014-01-13T01:56:35Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-Input LUTs # Sequential Systems ## State Minimization of Completely Specified Machines ### Partition Tables ### Implication Tables ## State Minimization of Incompletely Specified Machines ### Implication Tables # Asynchronous Machines # Design of the D Flip-Flop # Advanced Topics ee288b38ba221cb3393be7c3c5a81b9a301a5973 692 691 2014-01-13T01:57:42Z Wdr 2 wikitext text/x-wiki # Boolean Algebra # Two-Level Combinational Logic Minimization ## K-Maps ## Quine-McCluskey ### Single Functions ### Single Functions with Don't Cares ### Multiple-Output Functions ### Multiple-Output Functions with Don't Cares # Decomposition # Technology Mapping to K-Input LUTs # Sequential Systems ## State Minimization of Completely Specified Machines ### Partition Tables ### Implication Tables ## State Minimization of Incompletely Specified Machines ### Implication Tables # Asynchronous Machines # Metastability # Design of the D Flip-Flop # Advanced Topics 440f18e42c7bd3130077125d7b59bfd84734612e 0 46 694 482 2014-01-13T16:22:43Z Wdr 2 wikitext text/x-wiki *[[media:2012EvaluationReport.pdf|2012 CSE 460T Course Evaluation]] *[[media:Espresso.zip|Espresso for DOS]] *[[media:Edwin_Robbins.jpg|View from Edwin Robbins' Window]] 3bfa69c6a9c73620198edd7d0141529d3eb90284 696 694 2014-01-13T16:35:42Z Wdr 2 wikitext text/x-wiki *[[media:2012EvaluationReport.pdf|2012 CSE 460T Course Evaluation]] *[[media:Espresso.zip|Espresso for DOS]] *[[media:Xor.txt|XOR Gate Espresso Source]] *[[media:Edwin_Robbins.jpg|View from Edwin Robbins' Window]] af133ef54e5552865ac0186c68cd8cb754e173f1 6 257 695 2014-01-13T16:35:01Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 258 697 2014-01-14T20:52:04Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 709 697 2014-01-16T21:55:29Z Wdr 2 uploaded a new version of "[[File:SYNTHESIS OF TWO-LEVEL CIRCUITS.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 698 673 2014-01-14T20:52:29Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] e8cd810ce5f7bb0be23e4fe9954a1f3438ebe888 699 698 2014-01-14T20:52:53Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 4ed9759ff9d3ccc43d6b2101300bb9b5003186c1 701 699 2014-01-15T17:11:51Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 824e96ba6f3db4a038ba89a93a01bb0a368ef981 703 701 2014-01-16T20:15:36Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 664d4b1c47801e45c54bfe1a47ea3190fbf4be93 705 703 2014-01-16T20:16:34Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] e47977ea2132bd72fd43eb002511f56dd0b9f064 712 705 2014-01-21T15:38:35Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] a398b39e84d8d5f539b52edda9f4089150c4b5d6 716 712 2014-01-21T17:51:40Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 960006a7f71e86b472c13726f759bea372b44249 717 716 2014-01-21T18:52:28Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 85c42c567b16c5ddfca71928e8e44bbd4273bd50 718 717 2014-01-21T19:47:20Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (ARCTAN FUNCTION)]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 09198eb8a235361f539c00836e9675e24e717c64 719 718 2014-01-21T19:48:40Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 7def590248685e202a2995eb784cec324b3fa086 720 719 2014-01-21T19:49:39Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] bb2aa3cb893eb9ac3868a59173b97f94884a8f29 721 720 2014-01-21T19:53:05Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 49c225d81ce214e12f077c04fe0921c039a2fc26 722 721 2014-01-21T19:58:00Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 81ebaa9c98695100bd4372e2db132000cc6d4905 723 722 2014-01-21T20:32:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken into 64 Outputs]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] e2d91e15b3b5636f4a47e7a3fe9d971d87859e91 724 723 2014-01-21T20:32:56Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 2c01150eb12fcc1bb5cf574664f217199f5b83f6 725 724 2014-01-21T21:08:03Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken into 64 Sections/Outputs Then Combined into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 010fef0b21edc0a8e332380226736b4db579d1be 726 725 2014-01-21T21:08:47Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 7d0185d2f574649a4aef93b87118fe82f1705cfa 727 726 2014-01-21T21:09:51Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 07b8a58c650ee109c7d6f5b4a40b8b1c9bd9053b 729 727 2014-01-22T16:12:29Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 7fdd75290b56d46f02f4cd982f70eae91dd343b4 730 729 2014-01-22T16:46:34Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 1c0bb1cda71b944fb61a164fe0509ef6f3a83716 731 730 2014-01-22T16:46:49Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 69f6418a76aa53b3b1b3ec465da46aab4f39a680 732 731 2014-01-22T17:08:10Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 4e33cc20fb38fb84a6bf2161ba55a7310f1b34eb 736 732 2014-01-22T21:08:42Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 91611902de37df0fdceb09a1df01e64bc310c2ec 737 736 2014-01-23T16:47:52Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example]] *[[media:EspressoOutput.txt|Espresso Example Output]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 18d7bc58724c4c4d8d3d56c87035cdfb85da953a 738 737 2014-01-23T18:45:59Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] cec9b976b975d2ef09a8ff883ed6df395b963868 6 259 700 2014-01-15T17:11:22Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 708 700 2014-01-16T21:55:07Z Wdr 2 uploaded a new version of "[[File:K Maps.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 260 702 2014-01-16T20:14:57Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 707 702 2014-01-16T21:54:47Z Wdr 2 uploaded a new version of "[[File:Quine-McCluskey.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 261 704 2014-01-16T20:16:06Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 706 704 2014-01-16T21:54:30Z Wdr 2 uploaded a new version of "[[File:Reduction Techniques.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 710 706 2014-01-21T15:35:58Z Wdr 2 uploaded a new version of "[[File:Reduction Techniques.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 262 711 2014-01-21T15:37:59Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 713 711 2014-01-21T15:42:19Z Wdr 2 uploaded a new version of "[[File:Don't Cares.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 714 713 2014-01-21T15:44:16Z Wdr 2 uploaded a new version of "[[File:Don't Cares.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 263 715 2014-01-21T17:51:15Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 206 728 531 2014-01-21T21:15:16Z Wdr 2 uploaded a new version of "[[File:Decomposition By Expansion.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 265 735 2014-01-22T21:07:58Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 266 739 2014-01-23T19:06:30Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 740 738 2014-01-23T19:14:14Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 92bee821b3a9a43638b7946d4fa61eb083433cb7 742 740 2014-01-23T19:15:10Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 9b3d9668576bf45fda8136217ed6006d0b5a6a68 743 742 2014-01-23T20:05:13Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] http://cadlab.cs.ucla.edu/~cong/papers/tcad-feb-2007.pdf *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] fbab054de4b7322b50386a716dda41af8482e106 744 743 2014-01-23T21:19:54Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits http://arantxa.ii.uam.es/~die/%5BLectura%20EDA%5D%20A%20tutorial%20on%20logic%20synthesis%20for%20lookup-table%20based%20FPGAs.pdf *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] http://cadlab.cs.ucla.edu/~cong/papers/tcad-feb-2007.pdf *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] f2674aa1f6e11c0ad1278747682c4793e6d455c3 745 744 2014-01-23T21:20:33Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] http://cadlab.cs.ucla.edu/~cong/papers/tcad-feb-2007.pdf *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] fbab054de4b7322b50386a716dda41af8482e106 746 745 2014-01-23T21:20:52Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] afe3250968f7138685e4022b7278becc3c19bfc3 747 746 2014-01-23T21:21:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 294dfaf2e4fed33d1655763ad5b48c8ed2ebe13f 749 747 2014-01-24T21:02:51Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf|Technology Mapping for Standard Cells] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] b5f870f69ced9e2aec32e47046e8974c28e9b8a5 750 749 2014-01-24T21:03:35Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 91bfa2aee24bf0be41327071e5c5fa90613950ce 755 750 2014-01-24T21:15:54Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 3ac12c4bc310af50d22772f466a8be02fc4430fe 757 755 2014-01-28T21:17:06Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 7edd88d0cdea3113bdcd747705d6085c844e22e2 767 757 2014-01-31T20:50:56Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 32447bdfaef471aa96e6b343d3401bbe36163775 769 767 2014-02-03T15:59:46Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 9a60f936e058db7fcaf5c7bff5fe4203b7937aff 773 769 2014-02-03T16:04:02Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] c9ae509034ad6ebc0591ff670c61e8eceae916b5 776 773 2014-02-04T16:46:34Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 8ccf8ac9ac6e567a491d144717b8d71900ecadbf 779 776 2014-02-05T17:01:11Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 30fcadc621f40e5df7bfc37d904af7dae60512f3 787 779 2014-02-10T16:36:10Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 9a17eac19812ca633c9d182e046484ee256e6fe3 791 787 2014-02-10T20:25:49Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 7644633c799567fa2bd26066014ab7b7bb9148d4 793 791 2014-02-10T20:28:03Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 01ecb6de97d6ef13db5e118a60027808d4c5ccd1 795 793 2014-02-10T20:31:42Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 2fec3153427d2efcef2e07055d6b5abad030a139 802 795 2014-02-18T20:14:25Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 028e5dcb021223147ddeed44796e37dabf972a28 804 802 2014-02-18T20:17:40Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example Synthesis Report 2 FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 9136ded8e1103090a90414117d0527c87a0e4797 805 804 2014-02-18T20:18:35Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] ab217585baea1e5d810489b5d7a9df5d152ae3c4 6 267 741 2014-01-23T19:14:40Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 268 748 2014-01-24T21:02:16Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 752 680 2014-01-24T21:12:28Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_2.pdf|Homework #2]] c5a22ec427514d42963e192db96403726e64f083 753 752 2014-01-24T21:13:05Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 30, 2014]] *[[media:Homework_2.pdf|Homework #2 Due February 2, 2014]] 27adec2b0a0e6779ea01424a56fa3a66ebc5dacd 754 753 2014-01-24T21:13:38Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_2.pdf|Homework #2 Due February 2, 2014]] 029afe48ee9db2503e62db1974f70e017e6ecb45 759 754 2014-01-29T16:07:22Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 2, 2014]] 19affa8cb11b296ff38e47208d4e1ef200aa2ed7 761 759 2014-01-29T16:48:30Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] 76e0132d73cd99efd0a394f2ed85e99b23d85bf0 762 761 2014-01-29T16:49:10Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_3.pdf|Homework #3 Due February 12, 2014]] cff14988789c73b5a7be57dca093387d9871b395 763 762 2014-01-29T16:49:40Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] a25420eef0d8166f4a716e13ace1fbcd7b065a09 778 763 2014-02-05T16:55:11Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] b1b2a24647de2cd271b661ccc6c240ba77fbe8cc 783 778 2014-02-10T16:04:44Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] 418a455dcc296553d1a4f90a31fc07444ec7435b 6 270 756 2014-01-28T21:15:50Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 5 764 690 2014-01-29T16:50:29Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Tuesdays and Thursdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Mondays and Wednesdays, 11:30 a.m. - 1:00 p.m., Lab Sciences 250 Mid-term Exam I: February 12, 2014 Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 33.33% each. Homework/quizzes are 0%. Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded by the instructor and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity. 42da7e62d15805e5e275de4fc77603fbd84ce5de 6 272 766 2014-01-31T20:49:58Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 273 768 2014-02-03T15:59:00Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 770 768 2014-02-03T16:00:35Z Wdr 2 uploaded a new version of "[[File:A tutorial on logic synthesis for lookup-table based FPGAs.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 771 770 2014-02-03T16:01:45Z Wdr 2 uploaded a new version of "[[File:A tutorial on logic synthesis for lookup-table based FPGAs.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 274 772 2014-02-03T16:03:24Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 276 775 2014-02-04T16:46:02Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 36 785 681 2014-02-10T16:21:07Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:Exam_1_Results.pdf|Exam #1 Results]] 9fb2cb503d9cc2f370692dea04aaecf02cee1f40 797 785 2014-02-13T01:57:57Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] 8041723b26b3e9c18e8f23214c7c920257d47efe 800 797 2014-02-18T17:03:17Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:Exam_1_Solution.pdf|Exam #1 Solution]] 50fb6d9575e7eb2214ede6f3413c0b9ebe3dc35d 6 281 790 2014-02-10T20:24:39Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 282 792 2014-02-10T20:27:01Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 283 794 2014-02-10T20:31:01Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 286 801 2014-02-18T20:12:48Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 287 803 2014-02-18T20:15:49Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 288 806 2014-02-18T20:25:42Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 807 805 2014-02-18T20:27:13Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 49ebf6ddcd61d0d5879e31c1234e0486fec706f3 808 807 2014-02-18T20:28:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 5ec86e7e55ba86e89666e539e8d527cebe613c29 809 808 2014-02-18T20:29:30Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 2a72ae29ab2593b071812b6a3effa110f56c725b 811 809 2014-02-18T21:13:36Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 4c1ed9b35b40f211a429b5488eeaa6c7467a280c 813 811 2014-02-18T21:31:09Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 885302f593f647525cbc0f6c296b51978f92d13d 819 813 2014-02-18T21:38:35Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 2407645abb699cedd3d377620d0db77b97dcced4 821 819 2014-02-19T16:47:48Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] ae8cd55f1f8bced86806f3d9b97ad712dcdb2c9b 830 821 2014-02-20T16:44:48Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] ca732d01be441805e3de720d7945f540f82de3f3 833 830 2014-02-20T16:51:34Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] be22591335b7dd7f5f400db658475995f1656788 836 833 2014-02-20T20:03:17Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant FSM With Five States From Class]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 85b5edcb5eafbaaffab6d15365b18111a823651b 838 836 2014-02-20T21:18:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant Figure 7.4 FSM With Five States From Class]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 34193fc2153ae742017fdfc1cb1f283150e06b19 840 838 2014-02-20T21:43:38Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant Figure 7.4 FSM With Five States From Class]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 598ee2bcf4f302f12e94bf4565658f349b692eaf 841 840 2014-02-20T21:44:06Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant Figure 7.4 FSM With Five States From Class]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 04117c97b1fe936e19eb6c42b7aed2e5abb15697 843 841 2014-02-20T21:45:19Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant Figure 7.4 FSM With Five States From Class]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 8e6b4f37404c55a144855990f12da44b3a57c113 845 843 2014-02-20T21:50:10Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 states)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|Redundant Figure 7.4 FSM With Five States From Class]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 5f39f4f82905eb617c56a7f01534d87993b92eb0 847 845 2014-02-20T21:54:03Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 9ab44c6a79538c3066e7eece36c6a84de4002d5a 853 847 2014-02-24T15:56:44Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 40ae45905826f5d806c925f2a7e1d35a2f7f853c 854 853 2014-02-24T15:58:10Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 264062a08b383a2689e85e34b5c4bb6d77543d8b 857 854 2014-02-25T20:06:32Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] d1d834afe570446588799408ff3ec4319165ab19 859 857 2014-02-25T20:26:40Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] d5b504ea965dbedafe41481bd8b28f8143838b0e 864 859 2014-02-26T17:16:36Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] eb44c7c49821adff7a08d0827b216b9178dbe24e 6 289 810 2014-02-18T21:12:40Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 290 812 2014-02-18T21:14:03Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 291 814 2014-02-18T21:34:53Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 292 815 2014-02-18T21:35:15Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 293 816 2014-02-18T21:35:24Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 295 818 2014-02-18T21:37:51Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 296 820 2014-02-19T16:47:27Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 822 820 2014-02-19T17:15:22Z Wdr 2 uploaded a new version of "[[File:State Equal Output Moore Example Fixed.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 823 822 2014-02-19T17:19:50Z Wdr 2 uploaded a new version of "[[File:State Equal Output Moore Example Fixed.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 825 783 2014-02-19T17:25:05Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] 4319aec06f9bd159bf1979dc69daeab65be609d7 849 825 2014-02-21T15:28:54Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] 59a702bccb024c6bec2466c355a2326688a0ba74 851 849 2014-02-24T15:28:31Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] b1a10d0575eeabba5bfdbd7af264364f4926ae6f 861 851 2014-02-25T20:38:36Z Wdr 2 wikitext text/x-wiki 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da39a3ee5e6b4b0d3255bfef95601890afd80709 6 227 834 596 2014-02-20T19:27:30Z Wdr 2 uploaded a new version of "[[File:Definitions and Theorems for Sequential Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 304 835 2014-02-20T20:02:07Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 837 835 2014-02-20T20:06:08Z Wdr 2 uploaded a new version of "[[File:Minimizing Completely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 305 839 2014-02-20T21:43:00Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 306 842 2014-02-20T21:44:37Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 307 844 2014-02-20T21:49:23Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 308 846 2014-02-20T21:52:47Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 311 856 2014-02-25T20:05:18Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 312 858 2014-02-25T20:25:51Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 314 863 2014-02-26T17:14:24Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 315 865 2014-02-26T17:16:55Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 868 861 2014-03-03T16:53:29Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] 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*[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9]] *[[media:Homework_10.pdf|Homework #10]] 0d0069e87cfbeeb5e2cc972a195d8268ab6af519 6 317 870 2014-03-04T16:54:18Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 873 870 2014-03-04T19:38:01Z Wdr 2 uploaded a new version of "[[File:BCP Reduction Techniques.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 871 864 2014-03-04T16:55:05Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] FINITE AUTOMATA *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 8f6886dc5f970fd5de74ed772f13f42661f28d39 872 871 2014-03-04T16:55:55Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 3114599a09479060c40cd6b1fa0c47a5b7d6d779 890 872 2014-03-19T16:22:25Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 7702f954ce610af9d426269030be4c8823d76bef 895 890 2014-03-21T15:22:43Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] be8c0f0f5d5bf7f48d197803543fd5af7145c607 898 895 2014-03-21T18:08:01Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 599954e233752a1c0f6c6d3241ab4106f1f7d35e 900 898 2014-03-21T20:11:20Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example.pdf|Prime Compatibles Example from Hachtel and Somenzi]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] da324844acbb7c2e6bc21299899c502dbb01b8c8 902 900 2014-03-24T15:55:23Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] ddab09782f381a6b5111402c05cd4dec0a51d43f 903 902 2014-03-24T15:56:06Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 8f8cdccc4f5fe30b027380b0c3d8e9335854fff3 924 903 2014-04-01T18:39:18Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:Metastability_Lecture.pdf|Metastability Lecture]] *[[media:Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 9bc2f7bdaeb835913ccb89d2cf716a0b39231e38 926 924 2014-04-01T18:42:45Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:Metastability_Lecture.pdf|Metastability Lecture]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] 8636de055fa76042399390ae544845571eae00e9 928 926 2014-04-01T20:42:14Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:Metastability_Lecture.pdf|Metastability Lecture]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 7883c481158c545b05ffceaa2a13683639c039f6 934 928 2014-04-02T16:03:18Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability Lecture]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 44d823b6d0532469e248045398033e96298ff933 936 934 2014-04-03T16:04:00Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 072c3490d292ccf039ff57dff6ffa57ac87867ff 938 936 2014-04-03T16:07:08Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:NOR_Latch.jpg|NOR Latch]] *[[media:NOR_LATCH.vhd|NOR Latch VHDL Description]] *[[media:Norlatchsim.pdf|NOR Latch VHDL Simulation]] *[[media:Clocked_NOR_Latch.jpg|Clocked NOR Latch]] *[[media:Edge-Triggered_D_Flip-Flop.jpg|Edge-Triggered D Flip-Flop]] *[[media:D_FLIP_FLOP.vhd|Edge-Triggered D Flip-Flop VHDL Description]] *[[media:Dflopsim.pdf|Edge-Triggered D Flip-Flop VHDL Simulation]] *[[media:Dflopsim2.pdf|Edge-Triggered D Flip-Flop VHDL Simulation with Hold Time Violation]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 2d195c2807361cecfd99c54846f16698321d0f2a 939 938 2014-04-03T16:08:04Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators.pdf|Oscillators]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] d93663ce33ecfe79cafad5ba15ac50c55e47dc27 941 939 2014-04-03T16:11:25Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 16c3ad9c0a55cccabc61d6a2683e98a19493be72 0 5 874 764 2014-03-04T19:38:53Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Tuesdays and Thursdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Mondays and Wednesdays, 11:30 a.m. - 1:00 p.m., Lab Sciences 250 Mid-term Exam I: February 12, 2014 Mid-term Exam II: March 26, 2014 Final Exam: April 23, 2014 Grading: Three exams, 33.33% each. Homework/quizzes are 0%. Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded by the instructor and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. Homework submitted for grading must be done on an individual basis, and students submitting a copy of work done by someone else for grading will be considered to have violated the course policy on academic integrity. 35286addb857f1ae425e6bf137511bbf72385805 6 228 877 621 2014-03-05T16:49:52Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 879 877 2014-03-06T15:59:39Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 880 879 2014-03-06T16:01:13Z Wdr 2 uploaded a new version of "[[File:Simplification of Incompletely Specified Machines.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 322 889 2014-03-19T16:20:59Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 324 894 2014-03-21T15:22:08Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 325 897 2014-03-21T18:07:05Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 326 899 2014-03-21T20:10:42Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 327 901 2014-03-24T15:55:01Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 36 908 800 2014-03-26T16:20:58Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:Exam_1_Solution.pdf|Exam #1 Solution]] *[[media:Seating_chart.pdf|Exam #2 Seating Chart]] 0f3d0776bb5a635c29500d07c6c9b00043ee796a 909 908 2014-03-26T16:21:22Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:Exam_1_Solution.pdf|Exam #1 Solution]] *[[media:SEATING_CHART.pdf|Exam #2 Seating Chart]] 324b03372bc3053a279e72c70ac4833967890264 910 909 2014-03-26T16:21:55Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:SEATING_CHART.pdf|Exam #2 Seating Chart]] 3f2003a86170cb59eb3722db565bd05264e42cbf 912 910 2014-03-28T14:20:15Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:SEATING_CHART.pdf|Exam #2 Seating Chart]] *[[media:460T_Exam_2_Stick_Diagram.pdf|Exams 1&2 Stick Diagram]] a6cd3a9fd9a5c355155b7f87d28f56d495e7d742 913 912 2014-03-28T14:20:40Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:SEATING_CHART.pdf|Exam #2 Seating Chart]] *[[media:460T_Exam_2_Stick_Diagram.pdf|Exams 1 & 2 Stick Diagram]] 9aae28b7b66b3e837099653ba6317f85bbf3a4cb 917 913 2014-03-31T16:13:24Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:SEATING_CHART.pdf|Exam #2 Seating Chart]] *[[media:460T_Exam_2_Stick_Diagram.pdf|Exams 1 & 2 Stick Diagram]] *[[media:Exam_2_Solution.pdf|Exam 2 Solution]] 486c6c87efaa932abbde308d8a58a7428fb3e933 6 245 923 649 2014-04-01T18:37:36Z Wdr 2 uploaded a new version of "[[File:Metastability Lecture.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 929 923 2014-04-02T14:18:59Z Wdr 2 uploaded a new version of "[[File:Metastability Lecture.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 333 925 2014-04-01T18:42:18Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 335 933 2014-04-02T16:02:07Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 336 937 2014-04-03T16:06:28Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 945 937 2014-04-03T19:40:26Z Wdr 2 uploaded a new version of "[[File:Introduction to Asynchronous Circuits.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 337 940 2014-04-03T16:10:55Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 942 940 2014-04-03T16:12:55Z Wdr 2 uploaded a new version of "[[File:Oscillators and Clock Distribution.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 944 942 2014-04-03T19:23:51Z Wdr 2 uploaded a new version of "[[File:Oscillators and Clock Distribution.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 8 2 943 461 2014-04-03T18:29:55Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://classes.engineering.wustl.edu/cse460/index.php/Main_Page | Zar Course Slides ** http://www.usb.org | USB Implementers Forum * navigation ** mainpage|mainpage-description ** portal-url|portal ** currentevents-url|currentevents ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES f56d7f995582aa7d5ece56c6f6b2f770a165fece 0 35 946 931 2014-04-04T15:45:02Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] 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Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] 62a6766e84c24b78f5731921a61a2b09d2235b17 957 948 2014-04-07T15:07:11Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] 498268b6c1c9a2d72e7d884c4a6503103306f45c 961 957 2014-04-08T18:48:06Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] 098c4149da6a5e56a61d20f5acda7f6e8549279c 963 961 2014-04-08T18:53:14Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] *[[media:Homework_12.pdf|Homework #12 Due April 16, 2014]] b991ae81fbd9e776551ad4c5bd3f7c90069715de 970 963 2014-04-10T19:04:21Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] *[[media:Homework_12.pdf|Homework #12 Due April 16, 2014]] *[[media:Homework_13.pdf|Homework #13 Due April 21, 2014]] 69e29551310c83342e789b2b992ee831d94ff3db 974 970 2014-04-14T15:28:57Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] *[[media:Homework_11_Solution.pdf|Homework #11 Solution]] *[[media:Homework_12.pdf|Homework #12 Due April 16, 2014]] *[[media:Homework_13.pdf|Homework #13 Due April 21, 2014]] d219f6831036f7cf1b9abc9d53e6f68e8dbd1e05 981 974 2014-04-15T19:28:34Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] *[[media:Homework_11_Solution.pdf|Homework #11 Solution]] *[[media:Homework_12.pdf|Homework #12 Due April 16, 2014]] *[[media:Homework_12_Solution.pdf|Homework #12 Solution]] *[[media:Homework_13.pdf|Homework #13 Due April 21, 2014]] 378af28c8e0ee390523e12143c0a6e8f52502d8f 998 981 2014-04-18T19:15:30Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] *[[media:Homework_11_Solution.pdf|Homework #11 Solution]] *[[media:Homework_12.pdf|Homework #12 Due April 16, 2014]] *[[media:Homework_12_Solution.pdf|Homework #12 Solution]] *[[media:Homework_13.pdf|Homework #13 Due April 21, 2014]] *[[media:Homework_13_Solution.pdf|Homework #13 Solution]] 0bbee77919f7a2852c45b18407b04f47ba49c4a4 1010 998 2014-12-29T20:00:16Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1 Due January 29, 2014]] *[[media:Homework_2.pdf|Homework #2 Due February 5, 2014]] *[[media:Homework_3.pdf|Homework #3 Due February 10, 2014]] *[[media:Homework_4.pdf|Homework #4 Due February 24, 2014]] *[[media:Homework_5.pdf|Homework #5 Due March 3, 2014]] *[[media:Homework_6.pdf|Homework #6 Due March 5, 2014]] *[[media:Homework_7.pdf|Homework #7 Due March 19, 2014]] *[[media:Homework_8.pdf|Homework #8 Due March 24, 2014]] *[[media:Homework_9.pdf|Homework #9 Due April 7, 2014]] *[[media:Homework_10.pdf|Homework #10 Due April 9, 2014]] *[[media:Homework_11.pdf|Homework #11 Due April 14, 2014]] *[[media:Homework_12.pdf|Homework #12 Due April 16, 2014]] *[[media:Homework_13.pdf|Homework #13 Due April 21, 2014]] 0ee4db4f61038e9832e0bc1f8d81b125668f77a5 6 339 949 2014-04-04T19:50:03Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 955 949 2014-04-04T20:04:28Z Wdr 2 uploaded a new version of "[[File:Designing the SR Latch.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 950 941 2014-04-04T19:50:42Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 4ecf4b8277ea9557d6d7a46e6ebc735f60e2d6c4 952 950 2014-04-04T19:52:47Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:CLOCKGATE.vhd|David M. Zar Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|David M. Zar Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] 76cb5639165c9927e8de25551341da48bda12f6f 953 952 2014-04-04T19:55:04Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:CLOCKGATE.vhd|Fundamental Mode Design Example VHDL]] *[[media:Clockgate.pdf|Fundamental Mode Design Example Simulation]] *[[media:Kohavi.pdf|State Assignment]] cb4cd0798881679ca237af7dd268cbdafde51c1a 954 953 2014-04-04T19:56:06Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Kohavi.pdf|State Assignment]] b043de295d25fc84ffcbef91d521e50e1530c402 965 954 2014-04-09T16:26:58Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered DFlip-Flop]] *[[media:Kohavi.pdf|State Assignment]] 02ad44cff2f1f826e04bb314adac094e27efc4ee 966 965 2014-04-09T16:27:20Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:Kohavi.pdf|State Assignment]] 45c2becf8ee65407fab9486e28d5f5ea28cdec29 982 966 2014-04-16T14:58:59Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:Kohavi.pdf|State Assignment]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/ILLIAC_II 2c1e3ee24e9f28d4f4ead109b4ce50c377b8675f 983 982 2014-04-16T14:59:54Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/ILLIAC_II 1014e7610dd38545cbab43de12b41035a31f0ba8 985 983 2014-04-16T15:01:36Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/ILLIAC_II *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] cd20acf159811ebec18fff7975b1b345fcece8e8 986 985 2014-04-16T15:03:01Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] 83d97f224c56410d0b5e66da1eff0146a202b3e1 987 986 2014-04-16T15:03:18Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] 9ae613128cd5f2ec6e33b99c999355c2ef522526 988 987 2014-04-16T15:05:44Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] b6f25cc41f76caac88192abb1457bcec061d8cc3 991 988 2014-04-16T15:24:07Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] f2585c54d93ad7ad995ffe88b1ef917785db9525 995 991 2014-04-18T18:01:11Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] 71e375a28417e1486ca4833d3742d5ebf4889fed 1000 995 2014-04-21T15:17:58Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] 8a0737672972fb33403a032c45e89ac0e0b5af4f 6 340 951 2014-04-04T19:52:11Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 969 951 2014-04-10T18:52:32Z Wdr 2 uploaded a new version of "[[File:Asynchronous.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 336 959 945 2014-04-08T18:39:12Z Wdr 2 uploaded a new version of "[[File:Introduction to Asynchronous Circuits.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 972 959 2014-04-11T20:28:01Z Wdr 2 uploaded a new version of "[[File:Introduction to Asynchronous Circuits.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 978 972 2014-04-14T19:18:06Z Wdr 2 uploaded a new version of "[[File:Introduction to Asynchronous Circuits.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 344 964 2014-04-09T16:26:17Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 968 964 2014-04-09T19:19:27Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 976 968 2014-04-14T18:39:04Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 977 976 2014-04-14T18:40:26Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 989 977 2014-04-16T15:10:35Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 992 989 2014-04-16T18:29:32Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 348 984 2014-04-16T15:00:33Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 349 990 2014-04-16T15:23:24Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 350 994 2014-04-18T18:00:24Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 996 994 2014-04-18T18:27:02Z Wdr 2 uploaded a new version of "[[File:Designing an Asynchronous Counter.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1005 996 2014-04-22T15:23:23Z Wdr 2 uploaded a new version of "[[File:Designing an Asynchronous Counter.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 352 999 2014-04-21T15:17:18Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1009 999 2014-04-24T15:58:33Z Wdr 2 uploaded a new version of "[[File:The Reflected Binary (Gray) Code.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 337 1006 944 2014-04-22T15:51:26Z Wdr 2 uploaded a new version of "[[File:Oscillators and Clock Distribution.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 36 1008 917 2014-04-23T14:32:54Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Page_1.pdf‎|Exam #1 Page 1]] *[[media:460T_Exam_1_Stick_Diagram.pdf|Exam #1 Results]] *[[media:460T_Exam_2_Stick_Diagram.pdf|Exams 1 & 2 Stick Diagram]] *[[media:SEATING_CHART.pdf|Exam #3 Seating Chart]] 60ba000ca140e0fd19db3504b1386ab3525a9a37 1011 1008 2014-12-29T20:03:36Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1.pdf‎|Exam #1]] da83f3dade6da830a154a4c530d5183bc57db147 0 46 1012 696 2014-12-29T20:06:34Z Wdr 2 wikitext text/x-wiki *[[media:2014EvaluationReport.pdf|2012 CSE 460T Course Evaluation]] *[[media:Espresso.zip|Espresso for DOS]] *[[media:Xor.txt|XOR Gate Espresso Source]] *[[media:Edwin_Robbins.jpg|View from Edwin Robbins' Window]] 84d7ad61ce77346caf8f5b4db711bfb65b4dfdab 1013 1012 2014-12-29T20:06:42Z Wdr 2 wikitext text/x-wiki *[[media:2014EvaluationReport.pdf|2014 CSE 460T Course Evaluation]] *[[media:Espresso.zip|Espresso for DOS]] *[[media:Xor.txt|XOR Gate Espresso Source]] *[[media:Edwin_Robbins.jpg|View from Edwin Robbins' Window]] 33e6c8100767e9b925b7f6e09f8e2800290b3cce 0 5 1014 874 2016-01-07T19:47:56Z Wdr 2 wikitext text/x-wiki Instructor, William D. Richard, Ph.D., Bryan Hall 307B, 314-935-4676, wdr@wustl.edu Office Hours: Mondays and Wednesdays, 1:00-3:00 p.m. or by appointment Course Web Page: http://classes.engineering.wustl.edu/cse460t Text: Logic Synthesis and Verification Algorithms by Hachtel and Somenzi Class Meeting: Tuesdays and Thursdays, 10:00 a.m. - 11:30 p.m., Duncker 101 Mid-term Exam I: TBD Mid-term Exam II: TBD Final Exam: TBD Grading: Three exams, 33.33% each. Homework/quizzes are 0%. Homework: Homework will be assigned weekly and is optional. Homework turned in at the start of class on the due date will be graded by the instructor and returned with a representative grade indicated, but scores will not be recorded. No late homework will be accepted for grading. Homework solutions will be posted after class on the due date. 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1092 1082 2016-04-14T14:40:42Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_1_Solution.pdf|Homework #1 Solution]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_2_Solution.pdf|Homework #2 Solution]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_3_Solution.pdf|Homework #3 Solution]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_4_Solution.pdf|Homework #4 Solution]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_5_Solution.pdf|Homework #5 Solution]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_6_Solution.pdf|Homework #6 Solution]] *[[media:Homework_7.pdf|Homework #7]] *[[media:Homework_7_Solution.pdf|Homework #7 Solution]] *[[media:Homework_8.pdf|Homework #8]] *[[media:Homework_8_Solution.pdf|Homework #8 Solution]] *[[media:Homework_9.pdf|Homework #9]] *[[media:Homework_9_Solution.pdf|Homework #9 Solution]] *[[media:Homework_10.pdf|Homework #10]] *[[media:Homework_10_Solution.pdf|Homework #10 Solution]] *[[media:Homework_11.pdf|Homework #11]] *[[media:Homework_11_Solution.pdf|Homework #11 Solution]] 595537d558d3cb6f8f7c20891d8cb5f1986e1120 0 1 1017 686 2016-01-19T03:46:24Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2014''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday 10-11:30 a.m.''' ---- Prerequisites: CSE 260M f2ad0394f64ef60854965d49b57bb5650574964f 1018 1017 2016-01-19T03:47:31Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2015''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday 10-11:30 a.m.''' ---- Prerequisites: CSE 260M e6a260d9e5f1355c847fbff72176402e642ee14c 1019 1018 2016-01-19T15:21:25Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460T''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2016''' '''William D. Richard, Ph.D.''' ---- '''Tuesday/Thursday 10-11:30 a.m.''' ---- Prerequisites: CSE 260M c838115285d0197ba567bca96be4396219625250 0 36 1036 1011 2016-02-15T15:55:23Z Wdr 2 wikitext text/x-wiki *[[media:2014_Exam_1_Solution.pdf‎|Practice Exam #1 Solution]] 649420b734b7015ad4b57f8d5009ac673ca18f1c 1038 1036 2016-02-23T15:25:27Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Solution.pdf‎|Exam #1 Solution]] 18578671f0ca9f5dd01c07740ac7c0e50e1b5c10 1061 1038 2016-03-31T14:28:12Z Wdr 2 wikitext text/x-wiki *[[media:Exam_1_Solution.pdf‎|Exam #1 Solution]] *[[media:Exam_2_Solution.pdf‎|Exam #2 Solution]] dd1d87e3487a50972d5067e374456eefb7d935d4 6 365 1047 2016-03-03T15:50:55Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 1048 1000 2016-03-03T15:52:07Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] 1ad24de9a39301b96e5cca023c28d7a873e5c5c7 1066 1048 2016-04-05T21:39:19Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] cdf23fc6cba21afd6ef13b2fb2f41e30d04b1986 1068 1066 2016-04-05T22:19:12Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] 7bbc03d0d01b3a4726763663df386d913fce9394 1086 1068 2016-04-13T17:56:04Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] 97d47038da6a8d78fd27765bf7d0c8758e0bf7b4 1089 1086 2016-04-13T17:59:51Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] *[[media:Fsmtest.pdf|Testing FSMs]] c98cd701f921efc5d9237ce61bc37a9c93968eeb 1091 1089 2016-04-13T18:02:16Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] FINITE AUTOMATA http://www.arl.wustl.edu/~mbecchi/files/becchi_conext2007.pdf ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] *[[media:Fsmtest.pdf|Testing FSMs]] *[[media:Bist.pdf|BIST]] d7070a99dc836f71b8af6d3e58359cac611f3a9d 1097 1091 2016-04-15T19:40:12Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] *[[media:Fsmtest.pdf|Testing FSMs]] *[[media:Bist.pdf|BIST]] 914414bbf2691b5816d8a91c9c5744365adc3477 1098 1097 2016-04-15T19:40:52Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] *[[media:Fsmtest.pdf|Testing FSMs]] *[[media:Bist.pdf|BIST]] bdd50a92ef6d7f03ced38ee5677f9d9dae150974 6 317 1058 873 2016-03-29T13:56:11Z Wdr 2 uploaded a new version of "[[File:BCP Reduction Techniques.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 372 1065 2016-04-05T21:37:48Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1071 1065 2016-04-06T18:44:16Z Wdr 2 uploaded a new version of "[[File:Designing a Sequence Detector.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1072 1071 2016-04-06T20:32:03Z Wdr 2 uploaded a new version of "[[File:Designing a Sequence Detector.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1078 1072 2016-04-07T19:31:27Z Wdr 2 uploaded a new version of "[[File:Designing a Sequence Detector.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 373 1067 2016-04-05T22:18:21Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 344 1076 992 2016-04-07T14:59:50Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1079 1076 2016-04-07T21:43:00Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 1084 1079 2016-04-12T14:33:03Z Wdr 2 uploaded a new version of "[[File:Designing the Edge-Triggered D Flip-Flop.pdf]]" wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 379 1087 2016-04-13T17:56:29Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 380 1088 2016-04-13T17:59:05Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 381 1090 2016-04-13T18:01:23Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 6 384 1099 2016-04-19T14:01:41Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 30 1100 1098 2016-04-19T14:02:53Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:CDC_Lecture_2016.pdf|David M. Zar 2016 Clock Domain Crossing Lecture]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture 2012]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] *[[media:Fsmtest.pdf|Testing FSMs]] *[[media:Bist.pdf|BIST]] a2705e4c59e1ba7f6c8010fd7c4decd46c2d3516 1104 1100 2016-04-26T20:32:26Z Wdr 2 wikitext text/x-wiki LOGIC MINIMIZATION *[[media:Standard_Cell.JPG|Standard Cell Example]] *[[media:K_Maps.pdf|Karnaugh Maps]] *[[media:SYNTHESIS_OF_TWO-LEVEL_CIRCUITS.pdf|Synthesis of Two-Level Circuits]] *[[media:Quine-McCluskey.pdf|Quine-McCluskey Example]] *[[media:Reduction_Techniques.pdf|UCP Reduction Techniques]] http://en.wikipedia.org/wiki/Petrick%27s_method *[[media:Don't_Cares.pdf|Don't Cares]] *[[media:MULTIPLE_OUTPUT_FUNCTIONS.pdf|Multiple Output Functions]] *[[media:ITERATED_CONSENSUS.pdf|Iterated Consensus]] *[[media:Boole’s_Expansion_Theorem.pdf|Boole's Expansion Theorem]] *[[media:Decomposition_By_Expansion.pdf‎|Decomposition By Expansion]] http://classes.engineering.wustl.edu/cse460/images/c/c0/Decomposition.pdf http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer *[[media:EspressoExample.txt|Espresso Example (Quine-McCluskey Example)]] *[[media:EspressoOutput.txt|Espresso Example Output (Quine-McCluskey Example)]] *[[media:CyclicExample.txt|Espresso Cyclic Example]] *[[media:CyclicOutput.txt|Espresso Cyclic Example Output]] *[[media:Arctanbit0.txt|Espresso Arctan Bit 0 Example]] *[[media:Arctanbit0output.txt|Espresso Arctan Bit 0 Example Output]] http://www.mosis.com/pages/design/flows/design-flow-scmos-kits *[[media:Technology_Mapping.pdf‎|Technology Mapping for Standard Cells]] *[[media:Example1.vhd|VHDL Example 1]] *[[media:Example1RTL.pdf|VHDL Example 1 Synthesized RTL Schematic Default Settings]] *[[media:Example1Technology.pdf|VHDL Example 1 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example2.vhd|VHDL Example 2 (Quine-McCluskey Example)]] *[[media:Example2RTL.pdf|VHDL Example 2 Synthesized RTL Schematic Default Settings]] *[[media:Example2Technology.pdf|VHDL Example 2 Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:Example3.vhd|VHDL Example 3 (12-bit Arctan Function)]] *[[media:Example4.vhd|VHDL Example 4 (12-bit Arctan Function MSB)]] *[[media:Example4Technology.pdf|VHDL Example 4 Xilinx Spartan 6 Technology Map Schematic Default Settings (1 LUT)]] *[[media:Example5.vhd|VHDL Example 5 (12-bit Arctan Function Bit 10)]] *[[media:Example5Technology.pdf|VHDL Example 5 Xilinx Spartan 6 Technology Map Schematic Default Settings (3 LUTs)]] *[[media:Example6.vhd|VHDL Example 6 (12-bit Arctan Function Bit 9)]] *[[media:Example6Technology.pdf|VHDL Example 6 Xilinx Spartan 6 Technology Map Schematic Default Settings (10 LUTs)]] *[[media:Example7.vhd|VHDL Example 7 (12-bit Arctan Function Bit 8)]] *[[media:Example7Technology.pdf|VHDL Example 7 Xilinx Spartan 6 Technology Map Schematic Default Settings (19/23 LUTs)]] *[[media:Example8.vhd|VHDL Example 8 (12-bit Arctan Function Bit 0)]] *[[media:Example8Technology.bmp|VHDL Example 8 Xilinx Spartan 6 Technology Map Schematic Default Settings (2869 LUTs)]] *[[media:Example9.vhd|VHDL Example 9 (12-bit Arctan Function Bit 0, Only Bit 0 Specified)]] *[[media:Example9Technology.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Default Settings (3121 LUTs)]] *[[media:Example9TechnologyPH.bmp|VHDL Example 9 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (2384 LUTs)]] *[[media:Example10.vhd|VHDL Example 10 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs)]] *[[media:Example10Technology.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Default Settings (87 LUTs)]] *[[media:Example10TechnologyPH.pdf|VHDL Example 10 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (64 LUTs)]] *[[media:Example11.vhd|VHDL Example 11 (12-bit Arctan Function Bit 0 Broken Into 64 Sections/Outputs Then Combined Into One Output)]] *[[media:Example11Technology.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Default Settings (115 LUTs, 7 Levels of Logic, 12.289 ns)]] *[[media:Example11TechnologyPH.pdf|VHDL Example 11 Xilinx Spartan 6 Technology Map Schematic Preserve Hierarchy/Optimize Area (85 LUTs, 6 Levels of Logic, 11.966 ns)]] *[[media:Bit_Zero_Optimal_LUTs.pdf|Bit Zero Optimal LUTS (85 LUTs Is Optimal)]] *[[media:A_tutorial_on_logic_synthesis_for_lookup-table_based_FPGAs.pdf|Francis Paper]] *[[media:Tcad-feb-2007.pdf|Cong Optimality Paper]] *[[media:Altera_vs_Xilinx.pdf|Altera vs. Xilinx]] *[[media:Xilinx_vs_Altera.pdf|Xilinx vs. Altera]] *[[media:Altera_Logic_Efficiency_Analysis.pdf|Altera Logic Efficiency Analysis]] *[[media:Altera_FPGA_Architecture_White_Paper.pdf|Altera FPGA Architecture White Paper]] *[[media:BDDs.pdf|Binary Decision Diagrams (BDDs)]] *[[media:Ieeetc86.pdf|Bryant Paper]] http://myvideos.stanford.edu/player/slplayer.aspx?coll=ea60314a-53b3-4be2-8552-dcf190ca0c0b&co=18bcd3a8-965a-4a63-a516-a1ad74af1119&o=true SEQUENTIAL SYSTEMS *[[media:State_Equal_Output_Moore_Example_Fixed.pdf|State Equal Output Moore Example]] *[[media:Stateequaloutput.vhd|State Equal Output Moore Example VHDL]] *[[media:StateEqualOutputSimulation.pdf|State Equal Output Moore Example Simulation]] *[[media:Stateequaloutputsynthesisreport.txt|State Equal Output Moore Example Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology.pdf|State Equal Output Moore Example Technology Map Schematic Default Settings]] *[[media:ISE_Simulator_Screenshot_1.png|ISE Screenshot: Generating Post Place-and-Route Simulation Model]] *[[media:ISE_Simulator_Screenshot_2.png|ISE Screenshot: Simulating Post Place-and-Route Simulation Model]] *[[media:StateEqualOutputSimulationWithTiming.pdf|State Equal Output Moore Example Post Place-and-Route Simulation]] *[[media:StateEqualOutputWithTiming2.png|State Equal Output Moore Example Post Place-and-Route Simulation 2]] *[[media:Stateequaloutput2.vhd|State Equal Output Moore Example 2 VHDL]] *[[media:StateEqualOutputSimulation2.pdf|State Equal Output Moore Example 2 Simulation]] *[[media:Stateequaloutputsynthesisreport2.txt|State Equal Output Moore Example 2 Synthesis Report FSM Encoding Algorithm = User]] *[[media:StateEqualOutputTechnology2.pdf|State Equal Output Moore Example 2 Technolgy Map FSM Encoding Algorithm = User]] *[[media:Stateequaloutput3.vhd|State Equal Output Moore Example 3 VHDL]] *[[media:StateEqualOutputSimulation3.pdf|State Equal Output Moore Example 3 Simulation]] *[[media:Stateequaloutputsynthesisreport3.txt|State Equal Output Moore Example 3 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology3.pdf|State Equal Output Moore Example 3 Technology Map Schematic Default Settings]] *[[media:Stateequaloutput4.vhd|State Equal Output Moore Example 4 VHDL]] *[[media:StateEqualOutputSimulation4.pdf|State Equal Output Moore Example 4 Simulation]] *[[media:Stateequaloutputsynthesisreport4.txt|State Equal Output Moore Example 4 Synthesis Report Default Settings]] *[[media:StateEqualOutputTechnology4.pdf|State Equal Output Moore Example 4 Technology Map Schematic Default Settings]] *[[media:FIGURE7DOT4.png|Figure 7.4 (4 States)]] *[[media:figure7dot4.vhd|Figure 7.4 VHDL Description Version 1]] *[[media:Example12Technology.pdf|Xilinx Spartan 6 Technology Map Schematic Default Settings]] *[[media:DefaultV1SynthesisReport.txt|Default Version 1 Synthesis Report]] *[[media:Figure7dot4.pdf|Version 1 ModelSim Simulation]] *[[media:figure7dot4v2.vhd|Figure 7.4 VHDL Description Version 2]] *[[media:DefaultV2SynthesisReport.txt|Default Version 2 Synthesis Report]] *[[media:figure7dot4v3.vhd|Figure 7.4 VHDL Description Version 3]] *[[media:DefaultV3SynthesisReport.txt|Default Version 3 Synthesis Report]] *[[media:FIGURE7DOT4THREESTATES.png|Figure 7.4 (3 States)]] *[[media:Figure7dot4v4.vhd|VHDL Description Version 4 (3 States)]] *[[media:Figure7dot4v4.pdf|Version 4 ModelSim Simulation]] *[[media:DefaultV4SynthesisReport.txt|Default Version 4 Synthesis Report]] *[[media:xst_v6s6.pdf|XST User Guide (See Page 276 for Compact State Encoding)]] *[[media:FIGURE7DOT4V5.png|Figure 7.4 (5 States)]] *[[media:Figure7dot4WithFiveStates.vhd‎|VHDL Description Version 5 (5 States)]] *[[media:DefaultV5SynthesisReport.txt|Default Version 5 Synthesis Report]] *[[media:Definitions_and_Theorems_for_Sequential_Machines.pdf|Definitions and Theorems for Sequential Machines]] *[[media:Definition_of_Prime_Compatible.pdf|Definition of Prime Compatible from Hachtel and Somenzi]] *[[media:Minimizing_Completely_Specified_Machines.pdf|Minimizing Completely Specified Machines]] *[[media:Simplification_by_Implication_Tables.pdf|Simplification of Completely Specified Machines by Implication Tables]] *[[media:Simplification_of_Incompletely_Specified_Machines.pdf|Simplification of Incompletely Specified Machines]] *[[media:Simplification_of_Incompletely_Specified_Machines_1.pdf|Simplification of Incompletely Specified Machines 1]] *[[media:Simplification_of_Incompletely_Specified_Machines_2.pdf|Simplification of Incompletely Specified Machines 2]] *[[media:Prime_Compatibles_Example_Revised.pdf|Prime Compatibles Example from Hachtel and Somenzi (Revised)]] *[[media:BCP_Reduction_Techniques.pdf|BCP Reduction Techniques]] *[[media:State_Assignment.pdf|State Assignment]] ASYNCHRONOUS CIRCUITS AND METASTABILITY *[[media:Cmos-clock-datasheet.pdf|MX045 Oscillator Datasheet]] *[[media:Oscillators_and_Clock_Distribution.pdf|Oscillators and Clock Distribution]] *[[media:How_Fast_Can_We_Clock_A_Circuit.pdf|How Fast Can We Clock A Circuit?]] *[[media:Metastability 1.pdf|Anomalous Behavior of Synchronizer and Arbiter Circuits]] *[[media:Metastability 2.pdf|Measured Flip-Flop Responses to Marginal Triggering]] *[[media:Metastability_Lecture.pdf|Metastability]] *[[media:CDC_Lecture_2016.pdf|David M. Zar 2016 Clock Domain Crossing Lecture]] *[[media:Zar_Metastability_Lecture.pdf‎|David M. Zar Metastability Lecture 2012]] *[[media:Cypress_2KX9_FIFO.pdf|Cypress 2Kx9 Sync FIFO]] *[[media:Introduction_to_Asynchronous_Circuits.pdf|Introduction to Asynchronous Circuits]] *[[media:Asynchronous.pdf|Asynchronous Circuits]] *[[media:Designing_the_SR_Latch.pdf|Designing the SR Latch]] *[[media:Designing_an_Asynchronous_Counter.pdf|Designing an Asynchronous Counter]] *[[media:Designing_a_Sequence_Detector.pdf|Designing a Sequence Detector]] *[[media:Kohavi_Text_Example.pdf|Kohavi Text Example]] *[[media:Designing_the_Edge-Triggered_D_Flip-Flop.pdf|Designing the Edge-Triggered D Flip-Flop]] *[[media:The_Reflected_Binary_(Gray)_Code.pdf|The Reflected Binary (Gray) Code]] *[[media:Cucs-033-94.pdf|Essential Hazards in Asynchronous Sequential Machines]] *[[media:AsynchArt.pdf|Asynchronous Design Methodologies: An Overview]] ASYNCHRONOUS CPUs http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU http://en.wikipedia.org/wiki/ILLIAC_II http://en.wikipedia.org/wiki/AMULET_microprocessor http://www.intellasys.net/templates/trial/content/S40C18_DataSheet.pdf *[[media:S40C18_DataSheet.pdf|SEAforth 40C18]] VERIFICATION *[[media:Test.pdf|Automatic Test Generation]] *[[media:Fsmtest.pdf|Testing FSMs]] *[[media:Bist.pdf|BIST]] ad8b06e89764eecdf1f16ad7752de0bbcf8b096a 6 385 1103 2016-04-26T20:31:46Z Wdr 2 wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 35 1105 1092 2017-05-02T19:08:54Z Wdr 2 wikitext text/x-wiki *[[media:Homework_1.pdf|Homework #1]] *[[media:Homework_2.pdf|Homework #2]] *[[media:Homework_3.pdf|Homework #3]] *[[media:Homework_4.pdf|Homework #4]] *[[media:Homework_5.pdf|Homework #5]] *[[media:Homework_6.pdf|Homework #6]] *[[media:Homework_7.pdf|Homework #7]] *[[media:Homework_8.pdf|Homework #8]] *[[media:Homework_9.pdf|Homework #9]] *[[media:Homework_10.pdf|Homework #10]] *[[media:Homework_11.pdf|Homework #11]] b93c076df28a40d9485669892778021cc40cba2c 0 36 1106 1061 2017-05-02T19:09:07Z Wdr 2 Blanked the page wikitext text/x-wiki da39a3ee5e6b4b0d3255bfef95601890afd80709 0 46 1107 1013 2017-05-02T19:10:16Z Wdr 2 wikitext text/x-wiki *[[media:Espresso.zip|Espresso for DOS]] *[[media:Xor.txt|XOR Gate Espresso Source]] *[[media:Edwin_Robbins.jpg|View from Edwin Robbins' Window]] 6f63401e461339fe4b3cafbce134ebd2bf856839 8 2 1108 943 2017-05-02T19:10:53Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://classes.engineering.wustl.edu/cse460/index.php/Main_Page | Zar Course Slides ** http://www.usb.org | USB Implementers Forum * navigation ** mainpage|mainpage-description ** recentchanges-url|recentchanges ** randompage-url|randompage ** helppage|help ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 2eb3c439548cc87cf8422c236146684169d4226c 1109 1108 2017-05-02T19:11:10Z Wdr 2 wikitext text/x-wiki * Information ** General Information|General Information ** Syllabus|Syllabus ** Graders|Graders * Resources ** Lecture Notes|Lecture Notes ** Homework|Homework ** Exams|Exams ** Downloads|Downloads ** Datasheets|Datasheets * Other Links ** http://classes.engineering.wustl.edu/cse460/index.php/Main_Page | Zar Course Slides ** http://www.usb.org | USB Implementers Forum * navigation ** mainpage|mainpage-description ** recentchanges-url|recentchanges ** randompage-url|randompage ** Mediawiki:Sidebar|Sidebar Content * SEARCH * TOOLBOX * LANGUAGES 5970e4e79ed7b72bc2c2b029f1ca215e855c9652 0 1 1110 1019 2017-07-31T22:29:58Z Wdr 2 wikitext text/x-wiki <center> <font size=6>'''CSE460dT''' '''SWITCHING THEORY''' </font> <font size=3> '''Spring 2016''' '''William D. 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